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M3062PT2-EPB User's Manual
(3) Timing Requirements
Table 4.7 and Figures 4.6 show timing requirements in memory expansion mode and microprocessor mode.
Table 4.7 Timing requirements
Symbol
tsu(DB-RD)
Data input setup time
tsu(RDY-BCLK)
RDY# input setup time
tsu(HOLD-BCLK)
HOLD# input setup time
th(RD-DB)
Data input hold time
th(BCLK-RDY)
RDY# input hold time
th(BCLK-HOLD)
HOLD# input hold time
td(BCLK-HLDA)
HLDA# output delay time
Common to "with wait" and "no wait" (actual MCU)
BCLK
tsu(HOLD-BCLK)
HOLD input
HLDA output
P0,P1,P2,P3,P4,
P5
- P5
0
2
Common to "with wait" and "no wait" (this product)
BCLK
tsu(HOLD-BCLK)
HOLD input
HLDA output
P0,P1,P2,P3,P4,
P5
- P5
0
2
Figure 4.6 Timing requirements
* Compared with an actual MCU, this product enters high-impedance state after a 0.5 cycle delay.
REJ10J0868-0200 Rev.2.00 January 16, 2006
Item
th(BCLK-HOLD)
td(BCLK-HLDA)
H i -Z
th(BCLK-HOLD)
td(BCLK-HLDA)
Hi-Z
Actual MCU
[ns]
Min.
Max.
50
40
50
0
0
0
40
td(BCLK-HLDA)
td(BCLK-HLDA)
4. Hardware Specifications
This product
[ns]
Min.
Max.
65
60
70
See left
See left
See left
See left
Page 81 of 102
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