Renesas M16C/30P User Manual page 80

M3062PT2-EPB User's Manual
Read timing
BCLK
td(BCLK-CS)
CSi
ADi
/DBi
td(BCLK-AD)
ADi
BHE
td(BCLK-ALE)
ALE
th(BCLK-ALE)
RD
Write timing
BCLK
td(BCLK-CS)
CSi
ADi
/DBi
td(BCLK-AD)
ADi
BHE
td(BCLK-ALE)
ALE
WR,
WRL,WRH
Figure 4.5 Memory expansion mode and microprocessor mode (2 wait, accessing external area and using multiplex bus)
REJ10J0868-0200 Rev.2.00 January 16, 2006
tcyc
tac3(RD-DB)
td(AD-ALE) th(ALE-AD)
tdz(RD-AD)
td(AD-RD)
td(BCLK-RD)
tcyc
td(AD-ALE) th(ALE-AD)
td(BCLK-DB)
td(AD-WR)
th(BCLK-ALE)
td(BCLK-WR)
Hi-Z
tsu(DB-RD)
th(RD-DB)
th(BCLK-RD)
th(WR-CS)
td(DB-WR)
th(WR-DB)
th(BCLK-WR)
4. Hardware Specifications
th(BCLK-CS)
th(RD-CS)
th(BCLK-AD)
th(RD-AD)
th(BCLK-CS)
th(BCLK-DB)
th(BCLK-AD)
th(WR-AD)
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