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M3062PT2-EPB User's Manual
(2) Multiplex Bus Timing
Table 4.3 and Figure 4.2 show the bus timing in memory expansion mode and microprocessor mode (2-wait, accessing
external area, using multiplex bus).
Table 4.3 Memory expansion mode and microprocessor mode (2-wait, accessing external area, using multiplex bus)
Symbol
td(BCLK-AD)
Address output delay time
th(BCLK-AD)
Address output hold time (BCLK standard)
th(RD-AD)
Address output hold time (RD standard)
th(WR-AD)
Address output hold time (WR standard)
td(BCLK-CS)
Chip-select output delay time
th(BCLK-CS)
Chip-select output hold time (BCLK standard)
th(RD-CS)
Chip-select output hold time (RD standard)
th(WR-CS)
Chip-select output hold time (WR standard)
td(BCLK-RD)
RD signal output delay time
th(BCLK-RD)
RD signal output hold time
td(BCLK-WR)
WR signal output delay time
th(BCLK-WR)
WR signal output hold time
td(BCLK-DB)
Data output delay time (BCLK standard)
th(BCLK-DB)
Data output hold time (BCLK standard)
td(DB-WR)
Data output delay time (WR standard)
th(WR-DB)
Data output hold time (WR standard)
td(BCLK-ALE)
ALE output delay time (BCLK standard)
th(BCLK-ALE)
ALE output hold time (BCLK standard)
td(AD-ALE)
ALE output delay time (Address standard)
th(ALE-AD)
ALE output hold time (Address standard)
td(AD-RD)
After address RD signal output delay time
td(AD-WR)
After address WR signal output delay time
tdz(RD-AD)
Address output floating start time
*1 Calculated by the following formula according to the frequency of BCLK.
×
9
0
5 .
10
[ns]
(
)
f
BCLK
*2 Calculated by the following formula according to the frequency of BCLK.
(
)
−
×
9
0
5 .
10
n
−
40
[ns] n: "2" for 2 wait
(
)
f
BCLK
*3 Calculated by the following formula according to the frequency of BCLK.
×
9
0
5 .
10
−
25
[ns]
(
)
f
BCLK
*4 Calculated by the following formula according to the frequency of BCLK.
×
9
0
5 .
10
−
12
[ns]
(
)
f
BCLK
REJ10J0868-0200 Rev.2.00 January 16, 2006
Item
4. Hardware Specifications
Actual MCU
This product
[ns]
Min.
Max.
Min.
25
4
See left
(*1)
(*4)
(*1)
(*4)
25
4
See left
(*1)
(*4)
(*1)
(*4)
25
0
See left
25
0
See left
40
4
See left
(*2)
See left
(*1)
(*4)
25
-4
See left
(*3)
See left
30
See left
0
See left
0
See left
8
[ns]
Max.
See left
See left
See left
See left
See left
See left
15
Page 74 of 102
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