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M3062PT2-EPB User's Manual
4.2 Access Timing
Because this product emulates some ports, access timings are different from those of the actual MCUs. Chapters 4.2.1 and
4.2.2 describe the access timing using this product.
4.2.1 Operation Timing of Memory Expansion Mode and Microprocessor Mode (Vcc1=Vcc2=5V)
(1) Separate Bus Timing
Table 4.2 and Figure 4.1 show the bus timing in memory expansion mode and microprocessor mode.
Table 4.2 Memory expansion mode and microprocessor mode (3-wait, accessing external area)
Symbol
td(BCLK-AD)
Address output delay time
th(BCLK-AD)
Address output hold time (BCLK standard)
th(RD-AD)
Address output hold time (RD standard)
th(WR-AD)
Address output hold time (WR standard)
td(BCLK-CS)
Chip-select output delay time
th(BCLK-CS)
Chip-select output hold time (BCLK standard)
td(BCLK-ALE)
ALE signal output delay time
th(BCLK-ALE)
ALE signal output hold time
td(BCLK-RD)
RD signal output delay time
th(BCLK-RD)
RD signal output hold time
td(BCLK-WR)
WR signal output delay time
th(BCLK-WR)
WR signal output hold time
td(BCLK-DB)
Data output delay time (BCLK standard)
th(BCLK-DB)
Data output hold time (BCLK standard)
td(DB-WR)
Data output delay time (WR standard)
th(WR-DB)
Data output hold time (WR standard)
*1 Calculated by the following formula according to the frequency of BCLK.
(
)
−
×
9
0
5 .
10
n
−
40
[ns] n: "3" for 3 wait
(
)
f
BCLK
*2 Calculated by the following formula according to the frequency of BCLK.
×
9
0
5 .
10
[ns]
(
)
f
BCLK
*3 Calculated by the following formula according to the frequency of BCLK.
×
9
0
5 .
10
−
6
[ns]
(
)
f
BCLK
REJ10J0868-0200 Rev.2.00 January 16, 2006
Item
4. Hardware Specifications
Actual MCU
This product
[ns]
Min.
Max.
Min.
25
4
See left
0
-4
(*2)
(*3)
25
4
See left
25
-4
See left
25
0
See left
25
0
See left
40
4
See left
(*1)
See left
(*2)
See left
[ns]
Max.
See left
See left
See left
See left
See left
See left
Page 72 of 102
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