M3A-Hs60 Memory Mapping - Renesas M3A-HS60 User Manual

Renesas cpu board user's manual
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1.7 M3A-HS60 Memory Mapping

Figure1.7.1 shows the memory mapping example of SH7206 in the M3A-HS60.
Logical address
H'0000 0000
H'003F FFFF
H'0400 0000
H'0800 0000
H'0C00 0000
H'0CFF FFFF
H'0DFF FFFF
H'1000 0000
H'1400 0000
H'1800 0000
H'1C00 0000
H'2000 0000
H'4000 0000
H'8000 0000
H'FFF8 0000
H'FFFA 0000
H'FFFC 0000
H'FFFF FFFF
Note: There is the cacheable area from H'0000 0000~H'1FFF FFFF.
Rev.1.00 June 1,2005
REJ11J0002-0100Z
Logical space of theSH7206
CS0 space:64MB
CS1 space:64MB
CS2 space:64MB
CS3 space:64MB
CS4 space:64MB
CS5 space:64MB
CS6 space:64MB
CS7 space:64MB
CS0-CS7 spaces
(non-cacheable area)
CS8 space:1GB
Reserved area
(Disabled)
Internal RAM(128KB)
Internal RAM, Reserved
Internal peripheral module
Figure1.7.1 Memory Mapping Example of SH7206
1.7 M3A-HS60 Memory Mapping
Memory Mapping of theM3A-HS60
Flash Memory(4MB)
16-bit bus
User area
User area
User area
SDRAM(32MB)
SDRAM(16MB)
16-bit bus
32-bit bus
User area
User area
User area
User area
Reserved area
(Disabled)
Reserved area
(Disabled)
CS0-CS7 spaces
(non-cacheable area)
User area
Reserved area
(Disabled)
Internal RAM(128KB)
Internal RAM, Reserved
Internal peripheral module
Overview
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