Renesas M3A-HS60 User Manual page 19

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Table2.3.2 Examples for Bus State Controller Settings (Flash Memory Write/Read)
User Area Applicable Device
CS0 M5M29KT331AVP
<Write and Read Timing>
Write1
Th T1 Tw1 Tw2
CKIO
tAD1
A21-A1
tCSD1
CS0#
RD#
tWED1
tCS
tAS
WE0#
tDS
tWDD1
D15-D0
Rev.1.00 June 1,2005
REJ11J0002-0100Z
2.3.2 Flash Memory M5M29KT331AVP (included as standard equipment)
CS0 Space Bus Control Register : CS0BCR
Initial value : H'36DB 0600(when MD2= H and MD0=L）
Recommended set value : H'1000 0400
• Specify idle state in write to read and write to write intervals
IWW[2:0] = B'001: 1 idle cycles inserted
• Specify data bus
BSZ[1:0] = B'10 : 16-bit bus width
CS0 Space Wait Control Register (CS0WCR)
Initial value: H'0000 0500
Recommended set value : H'0000 0AC1
• Address, CS0# assert -> RD#, WEn# assert delay cycle
SW[1:0] = B'01 : 1.5 cycles
• Specify access wait cycles
WR[3:0] = B'0110 : 5 cycles
• RD#, WEn# negate -> Address, CS0 negate delay cycle
HW[1:0] = B'01 : 1.5 cycles
Tw3 Tw4 Tw5 T2 Tf Taw1 Th T1
tWC tWC tAD1
tAD1
tCSD1
tCSD1
tWED1
tWPH tWPH
tWP tWP tAH
tCH
tWDH1
tDH tWDD1
DATA
Figure2.3.2 Flash Memory Read and Write Access Timing
Bus State Controller Settings
Write2
Tw1 Tw2 Tw3 Tw4 Tw5 T2 Tf Taw1
tAD1
tCSD1
tWED1 tWED1
tOEH
tWP tWP tCH
tAS tAH
tDS tWDH1
tDH
DATA
Functional Overview
Read1
Th T1 Tw1 Tw2 Tw3 Tw4 Tw5 T2
tAD1
tRC tRC
tCSD1
tRSD
ta(OE)
ta(AD)
ta(CE1) tRDS1
DATA
Tf
tAD1
tCSD1
tRSD
tRDH1
tDF(OE)
2-5