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2
2.8 Reset Module
This module controls the reset signals connected to both the SH7206 and Flash memory mounted in the M3A-HS60.
Figure2.8.1 shows a block diagram of the reset module in M3A-HS60.
ResetIC output delay time,td=0.34 x Cd(pF)µsec = 34ms
ResetIC output detection voltage,Vs = 1.25 x
3.3V
Reset IC
Ra
10KW
M51957BFP
Input
Delay capacitance
Rb
10KW
*
Open-collector output
2.9 Interrupt Switches
As for the M3A-HS60, both the SH7206's NMI interrupt pin and MRES pin have a push switch connected. MRES switch
can be used for controlling manual reset for SH7206. When manual reset is done, the internal condition of CPU will be
formatted, but each register of on-chip peripheral module.
Figure2.9.1 shows a block diagram of interrupt switches.
NMI switch
MRES switch
Rev.1.00 June 1,2005
REJ11J0002-0100Z
)
)
Ra+Rb
= 2.5V
Rb
3.3V
*
Output
Cd
0.1µF
Reset switch
SW 2
Figure2.8.1 Block Diagram of Reset Module
3.3V
SW 5
3.3V
SW 6
Figure2.9.1 Block Diagram of Interrupt Switches
Functional Overview
2.8 Reset Module
H-UDI connector
RES#
Flash memory
RP#
Extension connector
RESET#
SH7206
RES#
SH7206
NMI#
MRES#/PE13
2-14
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