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2
2.3.3 External SDRAM
The M3A-HS60 includes two pcs. of 16-Mbyte SDRAM (for an external SDRAM) as standard equipment.
The SH7206's internal bus state controller can be used to control the SDRAM.
Note that the SDRAM can be switched between 32-bit bus access and 16-bit bus access. (For 16-bit bus access, only
one pc. of 16-Mbyte SDRAM can be used.)
Table2.3.3 lists SDRAM specifications used in M3A-HS60. Figure2.3.3 shows a block diagram of SDRAM.
Specification
Part number
Configuration
Capacity
Access time
CAS latency
Refresh interval
Row address
Column address
Number of banks
SDRAM
bus size setting
SDRAM_SZ
SH7206
14
A15-1
CS3#
DQMUU
DQMUL
CKIO
CKE
RD/WR#
RASL#
CASL#
DQMLU
DQMLL
Rev.1.00 June 1,2005
REJ11J0002-0100Z
Table2.3.3 SDRAM Specifications Used in M3A-HS60
EDS1216AATA-75E
16 Mbytes (16-bit bus width) x 2pcs.
32 Mbytes
5.4ns
2 (At 66MHz bus clock)
4,096 refresh cycles every 64ms
A11- A0
A8 - A0
4-bank operation controlled by BA0 and BA1
3.3V
SDRAM_SZ=Low:16-bit access using SDRAMx1
SDRAM_SZ=High:32-bit access using SDRAMx2
32-bit Access
A[13:2], A15-14
1OE#
2OE#
16-bit Access
A[12:1], A14-13
1OE#
2OE#
Figure2.3.3 Block Diagram of External SDRAM
Content
3.3V
EDS1216AATA
(8Mx16 bits)
14
MA11-0,BA1-0
16
CS#
DQ15-DQ0
DQMU
DQML
CLK
CKE
WE#
RAS#
CAS#
EDS1216AATA
(8Mx16 bits)
14
MA11-0,BA1-0
16
CS#
DQ15-DQ0
DQMU
DQML
CLK
CKE
WE#
RAS#
CAS#
Functional Overview
2.3.3 External SDRAM
SH72060 D31-D16
SH72060 D15-D0
2-6
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