Registers; List Of Registers - FUTABA FDP02TJ010 Instruction Manual

2.4ghz embedded type wireless modem
Table of Contents

Advertisement

7. Registers

All settings of the FDP02 are stored in its registers.

7.1. List of Registers

Below table shows list of all registers.
Register Function
REG00
Local station address
REG01 Group
address
Destination address of
REG02
Headerless-packet
REG03
Transmission mode
REG04
ID code 1
REG05
ID code 2
REG06
Frequency group
REG07
Frequency 1
REG08
Frequency 2
REG09
Frequency 3
REG10 Unused
REG11 Retransmission
REG12 Unused
Serial response of sent data
REG13
REG14 Unused
Command recognition interval
REG15
REG16 Unused
REG17
Buffer clear
Address check
REG18
REG19 Unused
Wired-communication setting 1
REG20
(serial communication)
Wired-communication setting 2
(flow control),
REG21
Low power stand-by mode,
Extended stand-by time
REG22
Low power stand-by time
Wired-communication setting 3
REG23
Delimiter for headerless-packet
transmission
REG24
Unit of sleep time duration
REG25
Sleep time
Time-out of headerless-packet
REG26
data input
* To initialize the registers, use the INI command (see Section 8.3.3) or input an initialization signal from the
/INI pin (see Section 9.1).
Default
00H
F0H
00H
F0H
00H
00H
03H
02H
2AH
51H
01H
frequency
0AH
00H
00H
00H
00H
00H
64H
8DH 8CH,
00H
00H
09H
04H
00H 00H,10H
C1H
04H
01H
Setting range
Remarks
00H to EFH
000 to 239
F0H to FEH
240 to 254
000 to 255 (to be used for headerless packet
00H to FFH
transmission)
F0H, FFH
Default: Packet transmission mode
00H to FFH
00H to FFH
01H to 03H
Default: 3-band mode
02H to 51H
Default: 2,402 MHz
02H to 51H
Default: 2,442 MHz
02H to 51H
Default: 2,481 MHz
-
00H to FFH
Default: 10 times
-
Default: "Returning P0 and P1 responses,"
00H to 07H
"Enabling N0 response," and "Enabling
response"
-
Default: 0 ms (to be used for headerless
00H to FFH
packet transmission)
-
01H to FFH
Default: 10s
Default: "Enabling destination address
8DH
check at reception"
-
Default: 9,600 bps, 8 data bits, no parity,
00H to FFH
and 1 stop bit
Default: "Disabling hardware flow control"
W
00H to FFH
Extended stand-by time is Zero
01H to FFH-
Default: 40ms
Default: "Not adding '<Cr><Lf>' to received
data" (to be used for headerless packet
transmission)
Default: <Cr><Lf> (to be used for
80Hto 83H
headerless packet transmission)
C0H to C4H
01H to FFH
Default: 40ms
Default: 10 ms (to be used for headerless
01H to FFH
packet transmission)
15
ithout low power stand-by mode
x 10ms
Ver.1.1

Advertisement

Table of Contents
loading

Table of Contents