Registers; List Of Registers - FUTABA FDP03TJ010 Instruction Manual

8. Registers

All settings of the FDP03 are stored in its registers.

8.1. List of Registers

Below table shows list of all registers.
Register Function
REG00 Local station address
REG01 Group address
Destination address of
REG02
Headerless-packet
REG03 Transmission mode
REG04 ID code 1
REG05 ID code 2
REG06 Frequency group
REG07 Frequency 1
REG08 Frequency 2
REG09 Frequency 3
REG10 Data transfer
REG11 Retransmission frequency
REG12 Unused
Serial response of sent data
REG13
REG14 Unused
Command recognition interval
REG15
REG16 Unused
REG17 Buffer clear
Address check
REG18
REG19 Unused
Wired-communication setting 1
REG20
(serial communication)
Wired-communication setting 2
(flow control),
REG21
Low power stand-by mode,
Extended stand-by time
REG22 Low power stand-by time
Wired-communication setting 3
REG23
Delimiter for headerless-packet
transmission
REG24
Unit of sleep time duration
REG25 Sleep time
Time-out of headerless-packet
REG26
data input
* To initialize the registers, use the INI command (see Section 8.3.3) or input an initialization signal from the
/INI pin (see Section 9.1).
Default Setting range
00H 00H to EFH
F0H F0H to FEH
00H 00H to FFH
F0H F0H, FFH
00H 00H to FFH
00H 00H to FFH
03H 01H to 03H
02H 02H to 4DH
2AH 02H to 4DH
4DH 02H to 4DH
01H 01H, 21H
0AH 00H to FFH
00H -
00H 00H to 07H
00H -
00H 00H to FFH
00H -
64H 01H to FFH
8DH 8CH, 8DH
00H -
00H 00H to FFH
09H 00H to FFH
04H 01H to FFH-
00H 00H,10H
80Hto 83H
C1H
C0H to C4H
04H 01H to FFH
01H 01H to FFH
17
Remarks
000 to 239
240 to 254
000 to 255 (to be used for headerless packet
transmission)
Default: Packet transmission mode
Default: 3-band mode
Default: 2,402 MHz
Default: 2,442 MHz
Default: 2,477 MHz
Default: Interchange mode
Default: 10 times
Default: "Returning P0 and P1 responses,"
"Enabling N0 response," and "Enabling
response"
Default: 0 ms (to be used for headerless
packet transmission)
Default: 10s
Default: "Enabling destination address
check at reception"
Default: 9,600 bps, 8 data bits, no parity,
and 1 stop bit
Default: "Disabling hardware flow control"
Without low power stand-by mode
Extended stand-by time is Zero
Default: 40ms
Default: "Not adding '<Cr><Lf>' to received
data" (to be used for headerless packet
transmission)
Default: <Cr><Lf> (to be used for
headerless packet transmission)
x 10ms
Default: 40ms
Default: 10 ms (to be used for headerless
packet transmission)
Ver.1.0