Pin Description - Advantech IDK-2117 Series User Manual

3.3

Pin Description

The module uses a pair of LVDS receivers- SN75LVDS82(Texas Instruments or simi-
lar). LVDS is a differential signal technology for LCD interface and high speed data
transfer device. The transmitter is a SN75LVDS83 (negative edge sampling) or com-
patible. The first LVDS port (RxOxxx) transmits odd pixels while the second LVDS
port (RxExxx) transmits even pixels.
Table 3.1: Pin Description
Pin No. Symbol
1 RxO0-
2 RxO0+
3 RxO1-
4 RxO1+
5 RxO2-
6 RxO2+
7 GND
8 RxOC-
9 RxOC+
10 RxO3-
11 RxO3+
12 RxE0-
13 RxE0+
14 GND
15 RxE1-
16 RxE1+
17 GND
18 RxE2-
19 RxE2+
20 RxEC-
21 RxEC+
22 RxE3-
23 RxE3+
24 GND
25 GND
26 NC
27 GND
28 VCC
29 VCC
30 VCC
Note: Input signals of odd and even clock shall be the same timing.
Description
Negative LVDS differential data input (Odd data)
Positive LVDS differential data input (Odd data)
Negative LVDS differential data input (Odd data)
Positive LVDS differential data input (Odd data)
Negative LVDS differential data input
(Odd data, H-Sync,V-Sync,DSPTMG)
Positive LVDS differential data input
(Odd data, H-Sync,V-Sync,DSPTMG)
Power Ground
Negative LVDS differential clock input (Odd clock)
Positive LVDS differential clock input (Odd clock)
Negative LVDS differential data input (Odd data)
Positive LVDS differential data input (Odd data)
Negative LVDS differential data input (Even data)
Positive LVDS differential data input (Even data)
Power Ground
Negative LVDS differential data input (Even data)
Positive LVDS differential data input (Even data)
Power Ground
Negative LVDS differential data input (Even data)
Positive LVDS differential data input (Even data)
Negative LVDS differential clock input (Even clock)
Positive LVDS differential clock input (Even clock)
Negative LVDS differential data input (Even data)
Positive LVDS differential data input (Even data)
Power Ground
Power Ground
No contact
Power Ground
+5.0V Power Supply
+5.0V Power Supply
+5.0V Power Supply
13 IDK-2117 User Manual