Timer 1; One 16-Bit Timer Mode (Timer 1); Overview; Function Description - Samsung S3C9228 User Manual

S3C9228/P9228_UM_REV1.10

TIMER 1

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TIMER 1

ONE 16-BIT TIMER MODE (TIMER 1)

The 16-bit timer 1 is used in one 16-bit timer or two 8-bit timers mode. If TACON.7 is set to "1", timer 1 is used as
a 16-bit timer. If TACON.7 is set to "0", timer 1 is used as two 8-bit timers.
— One 16-bit timer mode (Timer 1)
— Two 8-bit timers mode (Timer A and B)

OVERVIEW

The 16-bit timer 1 is an 16-bit general-purpose timer. Timer 1 has the interval timer mode by using the
appropriate TACON setting.
Timer 1 has the following functional components:
— Clock frequency divider (fxx divided by 512, 256, 64, 8, or 1, fxt, and T1CLK: External clock) with multiplexer
— 16-bit counter (TACNT, TBCNT), 16-bit comparator, and 16-bit reference data register (TADATA, TBDATA)
— Timer 1 match interrupt generation
— Timer 1 control register, TACON (page 0, BBH, read/write)

FUNCTION DESCRIPTION

Interval Timer Function
The timer 1 module can generate an interrupt: the timer 1 match interrupt (T1INT).
The T1INT pending condition should be cleared by software when it has been serviced. Even though T1INT is
disabled, the application's service routine can detect a pending condition of T1INT by the software and execute
it's sub-routine. When this case is used, the T1INT pending bit must be cleared by the application sub-routine by
writing a "0" to the INTPND2.0 pending bit.
In interval timer mode, a match signal is generated when the counter value is identical to the values written to the
timer 1 reference data registers, TADATA and TBDATA. The match signal generates a timer 1 match interrupt
and clears the counter.
If, for example, you write the value 32H and 10H to TADATA and TBDATA, respectively, and 8EH to TACON, the
counter will increment until it reaches 3210H. At this point, the timer 1 interrupt request is generated, the counter
value is reset, and counting resumes.
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