Fluke 6060B Instruction Manual page 102

THEORY OF OPERATION
R 198, and R200 provide isolation between the outputs. The VCO signal is coupled to the
output assembly A2A4 by a through-the-plate coaxial connector P 108 at the 0 dBm level.
The other VCO signal is connected to the divider lJ6l to provide the feedback for the
PLL.
3-49.
The sub-synthesizer consists of the clock generator, U34, 35, Q4, Q5, the gate-array, U33,
the divide by 500, U 1 5 , and lJ 1 6, and the low-pass filter L I I and L 1 7. Internal to the sub­
synthesizer gate-array, lJ33, are a divide-by-two, a 3 l / 2 decade-rate multiplier, and
associated latches.
The balanced 40-MHz
to a two-phase 20-MHz clock in lJ34, U35.
An enable output of each section allows multiple sections to be cascaded. The input
frequency to the rate-multiplier is 20-M Hz. The output frequency can be programmed
from zero to 19.995 MHz in 5-kHz steps. This signal is ORed with the other phase of the
20-M Hz clock to produce 20 M Hz to 39.995 M Hz at U 33 pin l . This is divided by two in
the gate-array, by ten in U l 5, and again by 50
5-Hz steps. This TTL signal at TP l l is filtered by L l l , L l 7 , and C4 l , C42, C48, C50, and
C5 l . Op-amp, U 10 forms an active q uadrature generator, and the output pins 14 and 8
are offset by 90°. These two signals are the 20-k Hz to 40-k Hz inputs for the Main PLL
single-sideband mixer.
3-50.
The VCO PCA A2A2 is the heart of the main PLL. It produces the signal that is further
processed to become the Signal Generator output. The VCO assembly is located in a
bottom side compartment of the Module section A2_
The VCO tunes over a frequency range of 490 M H z to 1050 M Hz with a control voltage
range of +2V to + l 8V. The basic oscillator circuit uses two active devices operating as
negative resistance clements. Coupled symmetrically to a resonator, each active device is
followed by a 6-dB amplifier and a 15-dB isolator pad that provides two coherent but
isolated signals at about 0 dBm.
One signal is sent to the Output A2A4 assembly, and the other to the Synthesizer A2Al
assembly. To suppress harmonics, two tuned trap filters are placed between the negative
resistance devices and amplifiers Q2 and Q4.
The oscillator transistors Q
and Q6. The voltage at the collectors of Ql and Q3 are typically set at +6V. The two 6-dB
amplifiers Q2 and Q4 are biased so that the voltage at their emitters is about +0.3V and at
their bases about + l V, with the collectors at about +6.5V.
The PLL control voltage from the Synthesizer assembly A2A l at P 102 provides the
tuning voltage for varactors CR
CR4 with resistors R6, R4, R 1 8, R l 9, and R20. These varactors, in conjunction with their
lead inductance and C l and C32, make up a shunt trap filter at twice the VCO frequency
to suppress the in-band second harmonic at both VCO outputs to typically less than -10
dBc.
The output attenuators consisting of R l 3 , R l 4, R l 5, R27, R28, and R29 provide the
isolation between the two VCO outputs at P 103 and P l 04. C23 and C30, in series with the
printed board inductors, form out-of-band trap filters for approximately 1 .4 G Hz_ These
filters further suppress the out-of-band harmonics.
3-18
SUB-SYNTHESIZER
ECL
clock signal is converted to TTL in Q4 and Q5, and converted
VCO PCA, A2A2
l
and Q3 are biased at 1 3 mA by the FET current sources Q5
l
and CR2. This voltage also controls varactors CR3 and
in
U 16 to produce 20 kHz to 39.995 kHz in
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