Fluke 6060B Instruction Manual page 101

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is stored in the VCO Calibration EPROM on the Controller board. For output
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frequencies above 5 1 2 MHz and below 245 MHz, the KV DAC setting is halved to
account for the effective frequency doubling that occurs on these bands.
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Range switching is provided by resistors R77, R78, R79, and FETs Q lO, Q l l , and Q l 2.
Comparator U42 converts TTL levels to OV (on), and -15V (off) required by the FETs.
U41A buffers the range switch, and in conjunction with R82, provides an overall FM
adjustment. At this point, the audio signal splits into two paths. The path that connects to
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the integrator, U41, is for modulation frequencies inside the loop bandwidth.
The path that sums with the VCO control voltage at J103 is for frequencies outside the
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loop bandw . idth. U4 1D is an active high-pass filter that compensates for the non-ideal
integrator and the ac coupling to the VCO tuning port.
The output of U41 D is summed with the VCO control voltage via R88 and Cl l7. FET
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Q 1 3 allows the FM to be turned off. The audio signal is also processed by integrator
U41 A, R85, R86, and C 1 15. The audio signal is ac coupled into the phase-detector
integrator via R89, R90, C l l 6, and FET Q14. (Resistor R90 adjusts the low frequency
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FM gain). This integrator makes the phase modulation produced at the Phase Detector
appear as FM.
800/40 MHZ PLL
I 3-47.
When the Signal Generator is operated in the low-band, the 800-MHz oscillator is locked
to the 10-MHz Reference and provides a local oscillator for the heterodyne circuit on the
Output PCA. It also provides a 40-MHz signal to the sub-synthesizer clock generator.
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The 800-MHz VCO is connected to the divide-by-four, U61, followed by a divide-by-five,
U62 and U63, providing 40 MHz to the sub-synthesizer clock generator through selector
I U 64. When the Signal Generator is not in the low-band, the 800-Hz oscillator and the first
divide-by-four are disabled by turning off Q28 (HET).
The 40-MHz Oscillator consisting of U64, L66, and CR24, is selected by U64. The 40-Hz
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balanced ECL signal from U 64 drives the two-phase clock generator. A self-biased gate,
U65, converts ECL to TTL. U66 divides the40-MHz signal by four to produce a 10-MHz
signal that is compared against the 10-MHz reference in the phase detector U59 and U65.
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Op-amp U60, resistor network Z9, and C I S ! , C l 85, C1 86, and C201 integrate the phase
detector pulses to produce a de control voltage for the 800-MHz VCO and the 40-MHz
vco.
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800-MHz VCO
3-48.
The 800-MHz VCO is a low noise, limited range, voltage-controlled oscillatorfor the 800-
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MHz PLL. The basic oscillator uses two active devices operating as negative resistance
elements, coupled symmetrically to a resonator made up of a varactor and an adjustable
capacitor. Each device is followed by an amplifier and isolation pad. This provides two
coherent outputs of +5 dBm to the PLL and 0 dBm to the output A2A4 assembly.
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The oscillator transistors Q32 and Q35 are biased at 1 3 rnA by R l 82 and R l 9 1 . The
voltage at the collectors of Q32 and Q35 is typically +2.5V. The tw o 6-dB amplifiers Q33
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and Q37 are biased so that the voltage at their emitters is about +0.3V, and the voltage at
their bases is about + I V with the collectors at +6.5V.
The PLL control voltage from U60 provides the tuning voltage for the varactor CR27.
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The adjustable capacitor C206 is set to provide +16V on the varactor to optimize the
VCO noise characteristic. The output attenuators consisting of R 186, R 187, R 189, R 197,
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THEORY OF OPERATION
3-17