Latch Counter - Mitsubishi Electric MELSEC iQ-R User Manual

Operation
The following shows operation of when the fixed cycle output start signal (input terminal 0) is input and when the fixed cycle
output stop signal (input terminal 1) is input.
High
Input terminal 0
Low
High
Input terminal 1
Low
High
Output terminal
Low
ON time
Performed in the flexible high-speed I/O control module
No. Description
(1) When a signal is input to the input terminal 0, pulse output starts. One pulse is output per cycle.
(2) When a signal is input to the input terminal 1, the pulse output stops.
4.7

Latch Counter

The current value is latched (held) as a latch count value.
The following describes a link and parameter example of a latch counter. With the example setting, when a rise of the latch
input signal is detected, the current value is latched. Note that this link example is for when a 32-bit unsigned multi function
counter block is used.
Link and parameter
The following shows a link example of the hardware logic outline window and a link example and parameter setting example
of the multi function counter block detail window.
■Hardware logic outline window
Phase A input pulse
Phase B input pulse
Latch signal
4 BLOCK LINK EXAMPLES
198
4.7 Latch Counter
(1)
1ms
(2)
Cycle time
1000ms