Mitsubishi Electric MELSEC iQ-R User Manual page 133

Flexible high-speed i/o control module
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Setting examples of the SSI encoder block
This section shows setting examples of the SSI encoder block suitable for a receive frame from the SSI encoder and
communication specifications.
■Multi turn
The following example is for the receive frame of a multi turn encoder. The receive frame consists of the elements below.
• Multi turn: 13 bits
• Single turn: 14 bits
• Status bit: 1 bit
• Parity bit: 1 bit
Clock
Most
significant bit
Receive frame
bit position
0
1
2
3
4
DATA
Multi turn start bit position
M12 M11M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
Multi turn: 13 bits
• Parameter
*1
Encoder specifications
Encoder type
Transmission speed
Monoflop time
*1 For details on the encoder specifications, refer to the manual for the encoder used.
• Parameters of "Data Frame Setting"
*2
Encoder specifications
Data type
Data frame length
Multi turn data length
Multi turn data start bit position
Encoder resolution
Single turn data length
Single turn data start bit position
Parity check
*2 For details on the encoder specifications, refer to the manual for the encoder used.
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Data frame length: 28 bits
SSI encoder block setting
Item
Multi turn
Encoder Type
1MHz
Transmission Speed
16s
Monoflop Time
Signal Error Detection
Direction
SSI encoder block setting
Item
Gray
Input Data Type
28 bits
Data Frame Length
13 bits
Multi Turn Data Length
0
Multi Turn Start Bit
16384
Encoder Resolution
14 bits
Single Turn Data Length
13
Single Turn Start Bit
Odd parity
Parity
Single turn: 14 bits
Remarks
Setting value
Multi Turn
1.0MHz
16
Enable
Set "Enable" to use the signal error detection.
Set "Disable" not to use it.
Forward
Set "Forward" to count the position data from
the SSI encoder in the forward direction. Set
"Reverse" to reverse the counting direction.
Remarks
Setting value
Gray code
28
The parity bit is not included.
13
0
Specify the receive frame bit position where
multi turn data starts.
0
Changing the setting value from its default (0) is
not required because the single turn data length
is 14 bits and the encoder resolution is 16384 (=
14
2
).
14
0
Setting is not required.
Odd
3 CREATING A HARDWARE LOGIC
3.1 Main Blocks in the Hardware Logic Outline Window
Least significant bit
S
P
Parity bit
Status bit: 1 bit
3
131

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