Operating Registers/Scripts Ram Read, 32-Bit - LSI LSI53C1510 Technical Manual

3.75 pc 10.25 pc
Table 7.20
Symbol
t
1
t
2
t
3
Figure 7.13 Operating Registers/SCRIPTS RAM Read, 32-Bit
(Driven by System)
FRAME/
(Driven by Master)
(Driven by Master-Addr;
LSI53C1510-Data)
(Driven by Master)
44.25 pc
(Driven by Master-Addr;
LSI53C1510-Data)
(Driven by Master)
(Driven by LSI53C1510)
(Driven by LSI53C1510)
DEVSEL/
(Driven by LSI53C1510)
11.25 pc

Operating Registers/SCRIPTS RAM Read, 32-Bit

Parameter
Shared signal input setup time
Shared signal input hold time
CLK to shared signal output valid
CLK
t
1
Addr In
t
1
AD
t
2
t
1
C_BE/
CMD
t
2
t
PAR
In
t
1
IRDY/
TRDY/
STOP/
PCI and External Memory Interface Timing Diagrams
34.5 pc
t
2
Byte Enable
1
t
2
t
3
Min Max
7 –
0 –
2 11
t
3
Data
Out
t
2
t
2
t
3
38.25 pc
4.333 pc
Unit
ns
ns
ns
t
3
Out
48.583 p
7-17
52.5 pc