Texas Instruments TMS320C2000 User Manual page 17

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or run-time information related to previous build levels. This allows a customer to commission system
software in a step-by-step manner, and at each step validate key vital signs before moving on. The
number of build levels may vary depending on final system complexity and the type of control strategy
used. It is important to note that regardless of the number of build levels used in the reference system, this
framework is provided by TI as guidance and becomes a common point of reference in cases where
customer trouble shooting necessitates interaction with TI customer support engineers.
Incremental system build levels are supported by frameworks with various configurations of interconnected
modules. Frameworks also provide invaluable skeletons for customers to modify or customize as required
to suit their own target system requirements, forming an excellent starting point.
To better understand the philosophy and details of the incremental build approach, a typical motor control
case, a permanent magnet synchronous motor, will be used to step through the various commissioning
phases. The system shown in is the final build of a sensored PMSM project. The subsequent block
diagrams (Figure 14
system.
2.4.1 Check System Vital Signs - Build Level 1
Figure 14 shows the module configuration of build level 1. Although the first is the simplest build, it is
perhaps the most important one since many system fundamentals can be validated here. Build 1 removes
main external connections (power hardware, motor, feedback circuitry, etc.) and allows a customer to
focus on:
• Code compiling/linking using a Code Composer Studio (CCS) project
• Invoking and downloading to the CCS debug environment
• Setting up or importing a CCS workspace
• Running code in real-time mode
• Ensuring the hardware is functioning correctly
Assuming the above check list is correct, some key system vital signs can now be validated:
• Check Interrupt Trigger: The sensored PMSM project, like most other DMC systems, is an interrupt
driven, time sampled system, meaning that the modules shown in
on every interrupt. The Isr_Ticker, a software variable in the interrupt subroutine (ISR) behaves like a
counter, and it is updated when an interrupt is triggered and the code in the ISR is executed. In order
to confirm that the ISR is being triggered at each selected event, this variable can be added to the
watch window to see whether or not it is updating.
• Testing some target independent modules: Validating both the stimulus waveforms (output of
RAMP_GEN), and output of SVGEN via the PWMDAC utility or graph windows confirms system
interrupts are being generated and the main ISR is executing correctly. At this stage, the RAMP_GEN
function can be manipulated via CCS watch window to change its frequency and to see the
corresponding changes on the waveforms.
• PWMDAC utility test: To monitor internal software variables and signal waveforms in real time PWM
DACs are very useful tools. Present on the HVDMC board are PWM DAC's (PWM5-7) which are
connected to external low pass filters to generate the waveforms. A simple 1st–order low-pass filter RC
circuit is placed on the board to filter out the high frequency components. The selection of R and C
value (or the time constant, t) is based on the cut-off frequency (fc). For example, R=1.8kΩ and
C=100nF, it gives fc = 884.2 Hz. This cut-off frequency has to be below the PWM frequency. Refer to
Using PWM Output as a Digital-to-Analog Converter on a TMS320F280x, SPRAA88A for more details.
• Check PWM outputs and verify PWM configuration: In addition, it is important to verify that the
space vector signals (Ta, Tb, and Tc) are correctly modulating the PWM outputs. This is easily
checked by filtering or suppressing the high frequency carrier (typically 10–20 kHz) at the PWM output
pins by a simple RC filter with approximately 1 kHz cutoff. The filtered waveforms should then
resemble the unmodulated ones seen at variables Ta, Tb, and Tc using the PWMDAC module. We
now have a working forward path for the PMSM controller running in open loop, and are ready to
connect the power inverter hardware and motor.
• Inverter test: After verifying SVGEN module, the PWM software module and the 3-phase inverter
hardware are tested by looking at the low pass filtered PWM outputs. For this purpose, if using the
external DC power supply, gradually increase the DC bus voltage and check the Vfb-U, V and W test
points using an oscilloscope; or if using AC power entry slowly change the variac to generate the DC
SPRUGI6 – September 2010
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to Figure 17) show examples of typical steps used to get to a solidly working final
Copyright © 2010, Texas Instruments Incorporated
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Figure 14 are executed and updated
TMS320C2000 Motor Control Primer
17