Message Interface Register Sets 1 And 2 - Texas Instruments TMS320F28004x Technical Reference Manual

Message Interface Register Sets
That being said, there is one condition that can cause a write access to the message RAM to be lost. If
MsgVal = 1 for the message object which is accessed and CAN communication is ongoing, a transfer from
the IFx register to message RAM may be lost. The reason for this is that it might happen that the IFx
register write to the message RAM occurs in between a read-modify-write access of the Host Message
Handler when it is in the process of receiving a message for the same message object.
To avoid this issue with receive mail boxes, reset MsgVal before changing any of the following: Id28-0,
Xtd, Dir, DLC3-0, RxIE, TxIE, RmtEn, EoB, Umask, Msk28-0, MXtd, and MDir.
To avoid this issue with transmit mail boxes, reset MsgVal before changing any of the following: Dir, RxIE,
TxIE, RmtEn, EoB, Umask, Msk28-0, MXtd, and MDir. Other fields not listed above, like Data, may be
changed without fear of losing a write to the message RAM.
NOTE: The CAN module uses a special addressing scheme to support byte accesses. For ease of
use, it is recommended to only make 32-bit accesses to the CAN registers. However, at
higher optimization levels, the compiler may split a 32-bit access into two sequential 16-bit
accesses, which will corrupt the register value. A compiler fix is in development. In the
meantime, 16-bit accesses can be used as a workaround. The lower 16 bits should be
written to the register's address, and the upper 16 bits should be written to the register's
address plus 2.

24.14.1 Message Interface Register Sets 1 and 2

The IF1 and IF2 register sets allow data transfers to and from the message objects. The IFxCMD register
for an interface control the direction of the data transfer. If the IFxCMD register is set to write, then the
message object fields selected by the IFxCMD register will be overwritten by values taken from the other
IFx registers. Is the IFxCMD register is set to read, then the message object fields selected by the
IFxCMD register will be copied from the message object to the other IFx registers. The interfaces allow for
transfers of a complete message object as well as individual parts. The transfer begins with the desired
message object number is written to bits 7:0 of the IFxCMD register.
When the CPU initiates a data transfer between the IF1/IF2 registers and Message RAM, the message
handler sets the Busy bit in the respective Command Register to '1'. After the transfer has completed, the
Busy bit is set back to '0' (see
2016
Controller Area Network (CAN)
Figure 24-15 ).
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SPRUI33 – November 4 2015 – Revised January 2017
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