Bit Time And Bit Rate - Texas Instruments TMS320F28004x Technical Reference Manual

Piccolo microcontrollers
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CAN Bit Timing
In many cases, the CAN bit synchronization will amend a faulty configuration of the CAN bit timing to such
a degree that only occasionally an error frame is generated. In the case of arbitration however, when two
or more CAN nodes simultaneously try to transmit a frame, a misplaced sample point may cause one of
the transmitters to become error passive.
The analysis of such sporadic errors requires a detailed knowledge of the CAN bit synchronization inside
a CAN node and of the CAN nodes' interaction on the CAN bus.
Even if minor errors in the configuration of the CAN bit timing do not result in immediate failure, the
performance of a CAN network can be reduced significantly.

24.13.1 Bit Time and Bit Rate

According to the CAN specification, the Bit time is divided into four segments (see
Synchronization Segment (Sync_Seg)
Propagation Time Segment (Prop_Seg)
Phase Buffer Segment 1 (Phase_Seg1)
Phase Buffer Segment 2 (Phase_Seg2)
Sync_
Seg
1 time quantum
Each segment consists of a specific number of time quanta. The length of one time quantum (t
the basic time unit of the bit time, is given by the CAN_CLK and the Baud Rate Prescalers (BRPE and
BRP). With these two Baud Rate Prescalers combined, divider values from 1 to 1024 can be programmed:
t
= Baud Rate Prescaler / CAN_CLK
q
Apart from the fixed length of the synchronization segment, these numbers are programmable.
describes the minimum programmable ranges required by the CAN protocol.
A given bit rate may be met by different bit time configurations.
Parameter
Sync_Seg
Prop_Seg
Phase_Seg1
Phase_Seg2
Synchronization Jump Width (SJW)
NOTE: For proper functionality of the CAN network, the physical delay times and the oscillator's
tolerance range have to be considered.
2008
Controller Area Network (CAN)
Figure 24-10. Bit Timing
Nominal CAN bit time
Prop_Seg
Phase_Seg1
(t
)
q
Table 24-4. Programmable Ranges Required by CAN Protocol
Range
1 t
(fixed)
q
[1 ... 8] t
q
[1 ... 8] t
q
[1 ... 8] t
q
[1 ... 4] t
q
Copyright © 2015–2017, Texas Instruments Incorporated
Phase_Seg2
Sample point
Remark
Synchronization of bus input to CAN_CLK
Compensates for the physical delay times
May be lengthened temporarily by synchronization
May be shortened temporarily by synchronization
May not be longer than either phase buffer segment
SPRUI33 – November 4 2015 – Revised January 2017
www.ti.com
Figure
24-10):
), which is
q
Table 24-4
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