The Propagation Time Segment - Texas Instruments TMS320F28004x Technical Reference Manual

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24.13.1.1 Synchronization Segment
The Synchronization Segment (Sync_Seg) is the part of the bit time where edges of the CAN bus level are
expected to occur. If an edge occurs outside of Sync_Seg, its distance to the Sync_Seg is called the
phase error of this edge.
24.13.1.2 Propagation Time Segment
This part of the bit time is used to compensate physical delay times within the CAN network. These delay
times consist of the signal propagation time on the bus and the internal delay time of the CAN nodes.
Any CAN node synchronized to the bit stream on the CAN bus can be out of phase with the transmitter of
the bit stream, caused by the signal propagation time between the two nodes. The CAN protocol's
nondestructive bitwise arbitration and the dominant acknowledge bit provided by receivers of CAN
messages require that a CAN node transmitting a bit stream must also be able to receive dominant bits
transmitted by other CAN nodes that are synchronized to that bit stream. The example in
shows the phase shift and propagation times between two CAN nodes.
Node B
Node A
Delay A_to_B >= node output delay(A) + bus line delay(AÆB) + node input delay(B)
Prop_Seg >= Delay A_to_B + Delay B_to_A
Prop_Seg >= 2 • [max(node output delay+ bus line delay + node input delay)]
In this example, both nodes A and B are transmitters performing an arbitration for the CAN bus. The node
A has sent its Start of Frame bit less than one bit time earlier than node B, therefore node B has
synchronized itself to the received edge from recessive to dominant. Since node B has received this edge
delay(A_to_B) after it has been transmitted, node B's bit timing segments are shifted with regard to node
A. Node B sends an identifier with higher priority and so it will win the arbitration at a specific identifier bit
when it transmits a dominant bit while node A transmits a recessive bit. The dominant bit transmitted by
node B will arrive at node A after the delay(B_to_A).
Due to oscillator tolerances, the actual position of node A's Sample Point can be anywhere inside the
nominal range of node A's Phase Buffer Segments, so the bit transmitted by node B must arrive at node A
before the start of Phase_Seg1. This condition defines the length of Prop_Seg.
If the edge from recessive to dominant transmitted by node B would arrive at node A after the start of
Phase_Seg1, it could happen that node A samples a recessive bit instead of a dominant bit, resulting in a
bit error and the destruction of the current frame by an error flag.
This error only occurs when two nodes arbitrate for the CAN bus which have oscillators of opposite ends
of the tolerance range and are separated by a long bus line; this is an example of a minor error in the Bit
timing configuration (Prop_Seg too short) that causes sporadic bus errors.
Some CAN implementations provide an optional 3 Sample Mode. The CAN does not. In this mode, the
CAN bus input signal passes a digital low-pass filter, using three samples and a majority logic to
determine the valid bit value. This results in an additional input delay of 1 t
SPRUI33 – November 4 2015 – Revised January 2017
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Figure 24-11. The Propagation Time Segment
Sync_Seg
Prop_seg
Delay A_to_B B_to_A
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Phase_seg2
Phase_seg1
Delay
, requiring a longer Prop_Seg.
q
Controller Area Network (CAN)
CAN Bit Timing
Figure 24-11
2009