Interrupts - Texas Instruments TMS320F28004x Technical Reference Manual

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Signal Name
Signal Name
RXCLK
RXD0
RXD1
(1)
Inactive level refers to the state of the pin while the module is not actively receiving data.
26.2.2.1 Configuring Device Pins
The GPIO mux registers must be configured to connect this peripheral to the device pins. To avoid
glitches on the pins, the GPyGMUX bits must be configured first (while keeping the corresponding
GPyMUX bits at the default of zero), followed by writing the GPyMUX register to the desired value.
Some IO functionality is defined by GPIO register settings independent of this peripheral. For input
signals, the GPIO input qualification should be set to asynchronous mode by setting the appropriate
GPxQSELn register bits to 0x3. The internal pullups can be configured in the GPyPUD register. See
General Purpose Input-Output,

26.2.3 Interrupts

Each FSI module contains multiple interrupt sources which can be assigned to two different interrupt
vectors: INT1 and INT2. Each interrupt source has an associated status flag, force, and clear bits in the
EVT_STS, EVT_FRC, and the EVT_CLR registers, respectively.
NOTE: Because the transmitter and receiver cores have their own distinct register sets, the
preceding 'TX_' and 'RX_' will be left off of the register names unless otherwise noted.
Each interrupt can be assigned to either interrupt vector, INT1 and INT2, to allow for two priority levels.
Alternately, the interrupt source can be prevented from generating any interrupt, though the status flag can
still be set and monitored by software. The transmitter events are assigned to either interrupt vector in the
TX_INT_CTRL register. The receiver events are assigned an interrupt vector using RX_INT1_CTRL and
RX_INT2_CTRL registers. If an interrupt is not required, ensure the bit is not set in the respective
INT_CTRL register.
26.2.3.1 Transmitter Interrupts
The transmitter can generate the following interrupts:
• Frame Done (FRAME_DONE)
This event indicates that has completed transmitting a frame.
• Buffer Underrun (BUF_UNDERRUN)
This event indicates that the transmit buffer has experienced underrun. Buffer underrun occurs when
the transmitter tries to read data from a location which has not yet be written to by the CLA, CPU, or
DMA.
SPRUI33 – November 4 2015 – Revised January 2017
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Table 26-1. FSI Transmitter Core Signals (continued)
Direction
During transmission, the data bits are split between TXD0 and
TXD1. TXD1 will contain all the odd numbered bits of the data
and CRC bytes. This applies only to the data words and the
CRC bytes. Other data frame related information like Frame
Type, Start-of-Frame, Tag and End-of-frame, the state of this
line will be identical to TXD0.
Table 26-2. FSI Receiver Core Signals
Direction
Input This is the receive clock input signal for the FSI receive module.
This must should be connected to TXCLK of the transmitting
FSI module.
Input This is the primary data input line for reception. This should be
connected to the TXD0 of the transmitting FSI module.
Input This is an additional data input line for reception. This signal
should be connected to the TXD1 of the transmitting FSI
module if multi-lane transmission is used.
Chapter 6, for more details on the GPIO mux and settings.
Copyright © 2015–2017, Texas Instruments Incorporated
Description
Description
Fast Serial Interface (FSI)
System-level Integration
(1)
Inactive Level
(1)
Inactive Level
Logic High
Logic High
Logic High
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