PCI-DAS4020/12 User's Guide
Dynamics and noise
SNR (Signal-to-noise ratio)
SINAD (signal-to-noise and distortion ratio)
SFDR (spurious free dynamic range)
THD (total harmonic distortion)
Noise distribution:
(Rate = 10 KHz-20 MHz, Average % ± 2 bins,
Average % ± 1 bin, Average # bins)
Trig/Ext Clk BNC
Software selectable for A/D Start Trigger (TRIG1), A/D Stop Trigger (TRIG2) or A/D Pacer Gate (AGATE);
also used as an A/D clock input 2X clock source (DAQ_CLK).
Input impedance
Input threshold
Input slew rate
Input range
Bandwidth
Coupling
Analog output
D/A converter type
Resolution
Number of channels
Output range
D/A pacing
Throughput
Data transfer
Monotonicity
Analog output drift
Settling time
(20 V step to ± ½ LSB)
Slew rate
Current drive
Output short-circuit
duration
Output coupling
Output impedance
Miscellaneous
Table 6. Dynamics and noise specifications
66.6 dB
66.5 dB
80 dB
80 dB
Bipolar (5V):
Bipolar (1V):
Table 7. Trig/Ext Clk BNC specifications
50 ohm, 1 Mohm selectable (coaxial cable termination)
Programmable 2.5 V threshold or 0 V threshold
1 V/µsec min
±5 V
40 MHz
DC
Table 8. Analog output specifications
AD7237
12-bits
2
±10 V, ±5 V software selectable
Software paced
System dependent. Using the Universal Library programmed output function (cbAout) in a
loop in Visual Basic, a typical update rate of 500 Hz (± 50 Hz) can be expected. The rate
was measured on a 330 MHz Pentium II based PC.
Programmed I/O
Guaranteed monotonic over temperature
±0.11 LSB/°C max, all ranges
5 µs max
5 V/µs
±5 mA
25 mA indefinite
DC
0.5 Ohm max
Single buffered output latch
Update DACs individually
On power-up and reset, the inputs to both D/A output buffers are grounded and the board's
D/A outputs will be set to 0 volts ± 6 mV. Upon writing to the D/A converters, the output
buffers will reflect the D/A outputs and achieve rated accuracy. However, upon writing a 0
to the D/A's, a small output change may be noted (up to 10 LSB).
100% / 98% / 5 bins
100% / 98% / 5 bins
24
Specifications
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