Siemens Simatic S7-1500 Manual page 43

Feedback interface per channel
The following table shows the feedback interface assignment:
Table 3- 4 Assignment of the feedback interface
Offset from start Parameter
address
Bytes 0 to 3 COUNT VALUE
Bytes 4 to 7 CAPTURED VALUE
Bytes 8 to 11 MEASURED VALUE
Byte 12 –
LD_ERROR
ENC_ERROR
POWER_ERROR
Byte 13 –
STS_SW_GATE
STS_READY
LD_STS_SLOT_1
LD_STS_SLOT_0
RES_EVENT_ACK
–
Byte 14 STS_DI2
STS_DI1
STS_DI0
STS_DQ1
STS_DQ0
STS_GATE
STS_CNT
STS_DIR
Byte 15 STS_M_INTERVAL
EVENT_CAP
EVENT_SYNC
EVENT_CMP1
EVENT_CMP0
EVENT_OFLW
EVENT_UFLW
EVENT_ZERO
CPU 1512C-1 PN (6ES7512-1CK00-0AB0)
Manual, 09/2016, A5E35306440-AB
Meaning
Current count value
Last Capture value acquired
Current measured value
Bits 3 to 7: Reserve; set to 0
Bit 2: Error when loading via control interface
Bit 1: Incorrect encoder signal
Bit 0: Incorrect supply voltage L+
Bits 6 to 7: Reserve; set to 0
Bit 5: Software gate status
Bit 4: Digital on-board I/O started up and parameters assigned
Bit 3: Load request for Slot 1 detected and executed (toggling)
Bit 2: Load request for Slot 0 detected and executed (toggling)
Bit 1: Reset of event bits active
Bit 0: Reserve; set to 0
Bit 7: Reserve; set to 0
Bit 6: Status HSC DI1
Bit 5: Status HSC DI0
Bit 4: Status HSC DQ1
Bit 3: Status HSC DQ0
Bit 2: Internal gate status
Bit 1: Count pulse detected within last approx. 0.5 s
Bit 0: Direction of last count value change
Bit 7: Count pulse detected in previous measuring interval
Bit 6: Capture event has occurred
Bit 5: Synchronization has occurred
Bit 4: Comparison event for DQ1 has occurred
Bit 3: Comparison event for DQ0 has occurred
Bit 2: Overflow has occurred
Bit 1: Underflow has occurred
Bit 0: Zero crossing has occurred
Technology functions
3.1 High-speed counters
43