Siemens Simatic S7-1500 Manual page 127

Hardware interrupts when using the high-speed counters
Table 6- 14 Hardware interrupts and their meaning
Hardware interrupt
Opening of the internal gate (gate
start)
Closing of the internal gate (gate
stop)
Overflow (high counting limit violat-
ed)
Underflow (low counting limit vio-
lated)
Comparison event for DQ0 oc-
curred
Comparison event for DQ1 oc-
curred
Zero crossing
New Capture value present
Synchronization of the counter by
an external signal
Direction reversal
2)
Can only be set in counting mode
1)
Feedback bit STS_DIR is preset to "0". When the first count value or position value change occurs in the reverse direc-
2)
tion directly after switching on the digital on-board I/O, a hardware interrupt is not triggered.
CPU 1512C-1 PN (6ES7512-1CK00-0AB0)
Manual, 09/2016, A5E35306440-AB
Event type Meaning
number
1 When the internal gate is opened, the technology function triggers a
hardware interrupt in the CPU.
2 When the internal gate is closed, the technology functions trigger a
hardware interrupt in the CPU.
3 When the count value exceeds the high counting limit, the technology
function triggers a hardware interrupt in the CPU.
4 When the count value falls below the low counting limit, the technology
function triggers a hardware interrupt in the CPU.
5 When a comparison event for DQ0 occurs due to the selected compari-
son condition, the technology function triggers a hardware interrupt in
the CPU.
When the change of the count value for an incremental or pulse encoder
was not caused by a count pulse, the technology function does not trig-
ger a hardware interrupt.
6 When a comparison event for DQ1 occurs due to the selected compari-
son condition, the technology function triggers a hardware interrupt in
the CPU.
When the change of the count value for an incremental or pulse encoder
was not caused by a count pulse, the technology function does not trig-
ger a hardware interrupt.
7 At a zero crossing of the counter or position value, the technology func-
tion triggers a hardware interrupt in the CPU.
8 When the current counter or position value is saved as a Capture value,
1)
the technology function triggers a hardware interrupt in the CPU.
9 At the synchronization of the counter by an N signal or edge at DI, the
technology function triggers a hardware interrupt in the CPU.
10 When the count value or position value changes direction, the technolo-
gy function triggers a hardware interrupt in the CPU.
Interrupts/diagnostics alarms
6.2 Interrupts and diagnostics
127