Instruction Set Summary - ARM Cortex-M4 Generic User Manual

3.1

Instruction set summary

Mnemonic Operands
ADC, ADCS {Rd,} Rn, Op2
ADD, ADDS {Rd,} Rn, Op2
ADD, ADDW {Rd,} Rn, #imm12
ADR Rd, label
AND, ANDS {Rd,} Rn, Op2
ASR, ASRS Rd, Rm, <Rs|#n>
B label
BFC Rd, #lsb, #width
BFI Rd, Rn, #lsb, #width
BIC, BICS {Rd,} Rn, Op2
BKPT #imm
BL label
BLX Rm
BX Rm
CBNZ Rn, label
CBZ Rn, label
-
CLREX
CLZ Rd, Rm
CMN Rn, Op2
CMP Rn, Op2
CPSID i
CPSIE i
ARM DUI 0553A
ID121610
The processor implements a version of the Thumb instruction set.
instructions.
Note
In Table 3-1:
• angle brackets, <>, enclose alternative forms of the operand
• braces, {}, enclose optional operands
• the Operands column is not exhaustive
• is a flexible second operand that can be either a register or a constant
Op2
• most instructions can use an optional condition code suffix.
For more information on the instructions and operands, see the instruction descriptions.
Brief description
Add with Carry
Add
Add
Load PC-relative Address
Logical AND
Arithmetic Shift Right
Branch
Bit Field Clear
Bit Field Insert
Bit Clear
Breakpoint
Branch with Link
Branch indirect with Link
Branch indirect
Compare and Branch if Non Zero
Compare and Branch if Zero
Clear Exclusive
Count Leading Zeros
Compare Negative
Compare
Change Processor State, Disable Interrupts
Change Processor State, Enable Interrupts
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Non-Confidential
The Cortex-M4 Instruction Set
Table 3-1 lists the supported
Table 3-1 Cortex-M4 instructions
Flags
N,Z,C,V
N,Z,C,V
-
-
N,Z,C
N,Z,C
-
-
-
N,Z,C
-
-
-
-
-
-
-
-
N,Z,C,V
N,Z,C,V
-
-
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3-2