Bfc And Bfi; Bit Field Clear And Bit Field Insert - ARM Cortex-M4 Generic User Manual

3.9.1

BFC and BFI

ARM DUI 0553A
ID121610

Bit Field Clear and Bit Field Insert.

Syntax
BFC{cond} Rd, #lsb, #width
BFI{cond} Rd, Rn, #lsb, #width
where:
Is an optional condition code, see
cond
Specifies the destination register.
Rd
Specifies the source register.
Rn
Specifies the position of the least significant bit of the bitfield.
lsb
range 0 to 31.
Specifies the width of the bitfield and must be in the range 1 to 32−
width
Operation
clears a bitfield in a register. It clears
BFC
Other bits in are unchanged.
Rd
copies a bitfield into one register from another register. It replaces
BFI
at the low bit position , with
lsb
unchanged.
Restrictions
Do not use SP and do not use PC.
Condition flags
These instructions do not affect the flags.
Examples
BFC R4, #8, #12
BFI R9, R2, #8, #12
Copyright © 2010 ARM. All rights reserved.
Non-Confidential
Conditional execution on page
bits in
width Rd
bits from starting at bit[0]. Other bits in
width Rn
; Clear bit 8 to bit 19 (12 bits) of R4 to 0
; Replace bit 8 to bit 19 (12 bits) of R9 with
; bit 0 to bit 11 from R2.
The Cortex-M4 Instruction Set
3-18.
must be in the
lsb
lsb
, starting at the low bit position
bits in
width
Rd
.
.
lsb
starting
Rd
are
3-115