Ap Encoding; Mpu Mismatch; Updating An Mpu Region; Updating An Mpu Region Using Separate Words - ARM Cortex-M4 Generic User Manual

AP[2:0]
000
001
010
011
100
101
110
111
4.5.7

MPU mismatch

4.5.8

Updating an MPU region

ARM DUI 0553A
ID121610
Table 4-46 shows the cache policy for memory attribute encodings with a TEX value is in the
range 4-7.
Table 4-47 shows the AP encodings that define the access permissions for privileged and
unprivileged software.
Privileged Unprivileged
permissions permissions
No access No access
RW No access
RW RO
RW RW
Unpredictable Unpredictable
RO No access
RO RO
RO RO
When an access violates the MPU permissions, the processor generates a MemManage fault, see
Exceptions and interrupts on page
MemManage Fault Status Register on page 4-25
To update the attributes for an MPU region, update the MPU_RNR, MPU_RBAR and
MPU_RASR registers. You can program each register separately, or use a multiple-word write
to program all of these registers. You can use the MPU_RBAR and MPU_RASR aliases to
program up to four regions simultaneously using an

Updating an MPU region using separate words

Simple code to configure one region:
; R1 = region number
; R2 = size/enable
; R3 = attributes
; R4 = address
LDR R0,=MPU_RNR
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Table 4-46 Cache policy for memory attribute encoding
Encoding, AA or BB
00
01
10
11
Description
All accesses generate a permission fault
Access from privileged software only
Writes by unprivileged software generate a permission fault
Full access
Reserved
Reads by privileged software only
Read only, by privileged or unprivileged software
Read only, by privileged or unprivileged software
2-10. The MMFSR indicates the cause of the fault. See
for more information.
; 0xE000ED98, MPU region number register
Cortex-M4 Peripherals
Corresponding cache policy
Non-cacheable
Write back, write and read allocate
Write through, no write allocate
Write back, no write allocate
Table 4-47 AP encoding
instruction.
STM
4-44