Ldr And Str, Immediate Offset - ARM Cortex-M4 Generic User Manual

3.4.2

LDR and STR, immediate offset

ARM DUI 0553A
ID121610
Load and Store with immediate offset, pre-indexed immediate offset, or post-indexed
immediate offset.
Syntax
op{type}{cond} Rt, [Rn {, #offset}]
op{type}{cond} Rt, [Rn, #offset]!
op{type}{cond} Rt, [Rn], #offset
opD{cond} Rt, Rt2, [Rn {, #offset}]
opD{cond} Rt, Rt2, [Rn, #offset]!
opD{cond} Rt, Rt2, [Rn], #offset
where:
Is one of:
op
Load Register.
LDR
Store Register.
STR
Is one of:
type
unsigned byte, zero extend to 32 bits on loads.
B
signed byte, sign extend to 32 bits (
SB
unsigned halfword, zero extend to 32 bits on loads.
H
signed halfword, sign extend to 32 bits (
SH
omit, for word.
-
Is an optional condition code, see
cond
Specifies the register to load or store.
Rt
Specifies the register on which the memory address is based.
Rn
Specifies an offset from
offset
Specifies the additional register to load or store for two-word operations.
Rt2
Copyright © 2010 ARM. All rights reserved.
Non-Confidential
The Cortex-M4 Instruction Set
; immediate offset
; pre-indexed
; post-indexed
; immediate offset, two words
; pre-indexed, two words
; post-indexed, two words
only).
LDR
Conditional execution on page
. If is omitted, the address is the contents of
Rn offset
only).
LDR
3-18.
3-24
.
Rn