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ARM Cortex R4F Technical Reference Manual

ARM Cortex R4F Technical Reference Manual (456 pages)

Cortex-R4 and Cortex-R4F Technical Reference Manual

Brand: ARM | Category: Processor | Size: 2 MB

Table of Contents

Change History
2
- Table of Contents
  3
- List of Tables
  7
- List of Figures
  13
Preface

16
- About this Book
  17
- Timing Diagrams
  19
- Key to Timing Diagram Conventions
  19
  - Further Reading
    20
  - Other Publications
    20
- Feedback
  21
- Feedback on this Product
  21
Chapter 1 Introduction

23
Chapter 2 Programmer's Model

47
- About the Programmer's Model
  48
- Instruction Set States
  49
- Operating Modes
  50
- Data Types
  51
- Memory Formats
  52
- Figure 2-1 Byte-Invariant Big-Endian (BE-8) Format
  52
- Figure 2-2 Little-Endian Format
  52
- Registers
  53
  - Stack Pointer
    53
  - Link Register
    53
- Table 2-1 Register Mode Identifiers
  54
- Figure 2-3 Register Organization
  55
- Program Status Registers
  56
- Figure 2-4 Program Status Register
  56
- Table 2-2 GE[3:0] Settings
  58
- Table 2-3 PSR Mode Bit Values
  60
- Exceptions
  62
  - Table 2-4 Exception Entry and Exit
    62
    
    Figure 2-5 Interrupt Entry Sequence
    67
    
    Data Aborts
    68
    
    Prefetch Aborts
    68
    
    Breakpoint Instruction
    71
  - Interrupt Request
    64
  - Interrupt Controller
    66
- Table 2-5 Configuration of Exception Vector Address Locations
  72
- Table 2-6 Exception Vectors
  72
- Acceleration of Execution Environments
  73
- Table 2-7 Jazelle Register Instruction Summary
  73
- Unaligned and Mixed-Endian Data Access Support
  74
- Big-Endian Instruction Support
  75
Chapter 3 Processor Initialization, Resets, and Clocking

76
- Initialization
  77
- Resets
  81
- Reset Modes
  82
  - Figure 3-1 Power-On Reset
    82
  - Table 3-1 Reset Modes
    82
  - Halt Operation
    83
  - Normal Operation
    83
  - Processor Reset
    83
- Clocking
  84
- Clock Gating
  84
- Figure 3-2 AXI Interface Clocking
  84
Chapter 4 System Control Coprocessor

85
Chapter 5 Prefetch Unit

160
- About the Prefetch Unit
  161
- Branch Prediction
  162
- Return Stack
  164
Chapter 6 Events and Performance Monitor

165
- About the Events
  166
  - Table 6-1 Event Bus Interface Bit Functions
    166
  - Table
    167
  - Table
    168
  - Table
    169
- About the PMU
  170
- Performance Monitoring Registers
  171
  - Figure 6-1 PMNC Register Format
    171
  - Table 6-2 PMNC Register Bit Functions
    171
  - Figure
    172
  - Table
    172
- Table 6-3 CNTENS Register Bit Functions
  173
- Figure 6-2 CNTENS Register Format
  173
- Table 6-4 CNTENC Register Bit Functions
  174
- Figure 6-3 CNTENC Register Format
  174
- Table 6-5 Overflow Flag Status Register Bit Functions
  175
- Figure 6-4 FLAG Register Format
  175
- Table 6-6 SWINCR Register Bit Functions
  176
- Figure 6-5 SWINCR Register Format
  176
- Figure 6-6 PMNXSEL Register Format
  176
- Table 6-7 Performance Counter Selection Register Bit Functions
  177
- Table 6-8 Evtselx Register Bit Functions
  178
- Figure 6-7 Evtselx Register Format
  178
- Table 6-9 USEREN Register Bit Functions
  179
- Figure 6-8 USEREN Register Format
  179
- Table 6-10 INTENS Register Bit Functions
  180
- Figure 6-9 INTENS Register Format
  180
- Table 6-11 INTENC Register Bit Functions
  181
- Figure 6-10 INTENC Register Format
  181
- Table
  183
- Event Bus Interface
  183
Chapter 7 Memory Protection Unit

184
- About the MPU
  185
  - Table 7-1 Default Memory Map
    185
  - Memory Regions
    186
  - Table
    186
  - Figure
    187
  - Table
    187
- Figure 7-1 Overlapping Memory Regions
  188
- Figure 7-2 Overlay for Stack Protection
  188
- Figure 7-3 Overlapping Subregion of Memory
  189
- Memory Types
  190
- Table 7-2 Memory Attributes Summary
  190
- Region Attributes
  192
- Table 7-3 TEX[2:0], C, and B Encodings
  192
- Table 7-4 Inner and Outer Cache Policy Encoding
  193
- MPU Interaction with Memory System
  194
- MPU Faults
  195
- Figure
  196
- MPU Software-Accessible Registers
  196
Chapter 8 Level One Memory System

197
- Figure
  198
- About the L1 Memory System
  198
- Figure 8-1 L1 Memory System Block Diagram
  199
- About the Error Detection and Correction Schemes
  200
  - Figure 8-2 Error Detection and Correction Schemes
    200
  - Error Checking and Correction
    201
  - Hard Errors
    201
  - Error Correction
    202
  - Table
    202
  - Table
    203
- Fault Handling
  203
  - Table
    204
  - External Faults
    204
  - Table
    206
  - Usage Models
    206
  - Correctable Errors
    207
- Table 8-1 Types of Aborts
  207
- Table
  209
- About the Tcms
  209
- Table
  211
- About the Caches
  214
- Store Buffer
  214
- Table 8-2 Cache Parity Error Behavior
  217
- Table 8-3 Cache ECC Error Behavior
  218
- Table 8-4 Tag RAM Bit Descriptions, with Parity
  222
- Table 8-5 Tag RAM Bit Descriptions, with ECC
  222
- Table 8-6 Tag RAM Bit Descriptions, no Parity or ECC
  222
- Table 8-7 Cache Sizes and Tag RAM Organization
  223
- Table 8-8 Organization of a Dirty RAM Line
  223
- Figure 8-3 Nonsequential Read Operation Performed with One RAM Access
  224
- Figure 8-4 Sequential Read Operation Performed with One RAM Access
  224
- Table 8-9 Instruction Cache Data RAM Sizes, no Parity or ECC
  225
- Table 8-10 Data Cache Data RAM Sizes, no Parity or ECC
  225
- Table 8-11 Instruction Cache Data RAM Sizes, with Parity
  225
- Table 8-13 Data Cache RAM Bits, with Parity
  226
- Table 8-14 Instruction Cache Data RAM Sizes with ECC
  226
- Table 8-12 Data Cache Data RAM Sizes, with Parity
  226
- Table 8-15 Data Cache Data RAM Sizes with ECC
  227
- Table 8-16 Data Cache RAM Bits, with ECC
  227
- Internal Exclusive Monitor
  230
- Memory Types and L1 Memory System Behavior
  231
- Table 8-17 Memory Types and Associated Behavior
  231
- Error Detection Events
  232
- Table
  233
Chapter 9 Level Two Interface

234
Chapter 10 Power Control

266
- About Power Control
  267
- Power Management
  268
  - Run Mode
    268
  - Standby Mode
    268
  - Shut down Mode
    268
Chapter 11 Debug

270
Chapter 12 FPU Programmer's Model

342
Chapter 13 Integration Test Registers

356
Chapter 14 Cycle Timings and Interlock Behavior

367
Chapter 15 AC Characteristics

401
Appendix A Processor Signal Descriptions

414
- Table
  415
- About the Processor Signal Descriptions
  415
- A.2 Global Signals
  416
- Global Signals
  416
- Table A-1 Global Signals
  416
- A.3 Configuration Signals
  417
- Configuration Signals
  417
- Table A-2 Configuration Signals
  417
- Table
  419
- Interrupt Signals, Including VIC Interface Signals
  420
- Table A-3 Interrupt Signals
  420
- A.5 L2 Interface Signals
  421
- L2 Interface Signals
  421
- Table A-4 AXI Master Port Signals for the L2 Interface
  421
- Table A-5 AXI Master Port Error Detection Signals
  423
- Table A-6 AXI Slave Port Signals for the L2 Interface
  423
- Table A-7 AXI Slave Port Error Detection Signals
  425
- TCM Interface Signals
  426
- Table A-8 ATCM Port Signals
  426
- Table A-9 B0TCM Port Signals
  426
- Table A-10 B1TCM Port Signals
  427
- Dual Core Interface Signals
  429
- Table A-11 Dual Core Interface Signals
  429
- Debug Interface Signals
  430
- Table A-12 Debug Interface Signals
  430
- Table A-13 Debug Miscellaneous Signals
  430
- ETM Interface Signals
  432
- Table A-14 ETM Interface Signals
  432
- A.10 Test Signals
  433
- Test Signals
  433
- Table A-15 Test Signals
  433
- A.11 MBIST Signals
  434
- MBIST Signals
  434
- Table A-16 MBIST Signals
  434
- A.12 Validation Signals
  435
- Validation Signals
  435
- Table A-17 Validation Signals
  435
  - Table A-18 FPU Signals
    436
  - A.13 FPU Signals
    436
- FPU Signals
  436
Appendix Becc Schemes

437
- ECC Scheme Selection Guidelines
  438
Appendix C Revisions

442
Glossary

442
- Addressing Modes
  442
- Rounding Mode
  453

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