Shsub16 And Shsub8 - ARM Cortex-M4 Generic User Manual

3.5.12

SHSUB16 and SHSUB8

ARM DUI 0553A
ID121610
Signed Halving Subtract 16 and Signed Halving Subtract 8.
Syntax
op{cond}{Rd,} Rn, Rm
where:
Is any of:
op
Signed Halving Subtract 16
SHSUB16
Signed Halving Subtract 8
SHSUB8
Is an optional condition code, see
cond
Specifies the destination register.
Rd
Specifies the first operand register.
Rn
Specifies the second operand register
Rm
Operation
Use these instructions to add 16-bit and 8-bit data and then to halve the result before writing the
result to the destination register:
The instruction:
SHSUB16
1. Subtracts each halfword of the second operand from the corresponding
halfwords of the first operand.
2. Shuffles the result by one bit to the right, halving the data.
3. Writes the halved halfword results in the destination register.
The instruction:
SHSUBB8
1. Subtracts each byte of the second operand from the corresponding byte of
the first operand,
2. Shuffles the result by one bit to the right, halving the data,
3. Writes the corresponding signed byte results in the destination register.
Restrictions
Do not use SP and do not use PC
Condition flags
These instructions do not change the flags.
Examples
SHSUB16 R1, R0 ; Subtracts halfwords in R0 from corresponding halfword
; of R1 and writes to corresponding halfword of R1
SHSUB8 R4, R0, R5 ; Subtracts bytes of R0 from corresponding byte in R5,
; and writes to corresponding byte in R4.
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The Cortex-M4 Instruction Set
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