Busfault Address Register; Auxiliary Fault Status Register; System Control Block Usage Hints And Tips - ARM Cortex-M4 Generic User Manual

4.3.13

BusFault Address Register

Bits Name
[31:0] ADDRESS
4.3.14

Auxiliary Fault Status Register

4.3.15

System control block usage hints and tips

ARM DUI 0553A
ID121610
When an unaligned access faults, the address is the actual address that faulted. Because a single
read or write instruction can be split into multiple aligned accesses, the fault address can be any
address in the range of the requested access size.
Flags in the MMFSR indicate the cause of the fault, and whether the value in the MMFAR is
valid. See MemManage Fault Status Register on page
The BFAR contains the address of the location that generated a BusFault. See the register
summary in Table 4-12 on page 4-11
Function
When the BFARVALID bit of the BFSR is set to 1, this field holds the address of the location that
generated the BusFault
When an unaligned access faults the address in the BFAR is the one requested by the instruction,
even if it is not the address of the fault.
Flags in the BFSR indicate the cause of the fault, and whether the value in the BFAR is valid.
See BusFault Status Register on page
The AFSR contains additional system fault information. See the register summary in
on page 4-11 for its attributes.
This register is read, write to clear. This means that bits in the register read normally, but writing
1 to any bit clears that bit to 0.
The bit assignments are:
Bits Name
[31:0] IMPDEF
Each AFSR bit maps directly to an AUXFAULT input of the processor, and a single-cycle
HIGH signal on the input sets the corresponding AFSR bit to one. It remains set to 1 until you
write 1 to the bit to clear it to zero. See your vendor documentation for more information.
When an AFSR bit is latched as one, an exception does not occur. Use an interrupt if an
exception is required.
Ensure software uses aligned accesses of the correct size to access the system control block
registers:
• except for the CFSR and SHPR1-SHPR3, it must use aligned word accesses
• for the CFSR and SHPR1-SHPR3 it can use byte or aligned halfword or word accesses.
The processor does not support unaligned accesses to system control block registers.
Copyright © 2010 ARM. All rights reserved.
Non-Confidential
for its attributes. The bit assignments are:
4-26.
Function
Implementation defined. The bits map to the AUXFAULT input signals.
Cortex-M4 Peripherals
4-25.
Table 4-30 BFAR bit assignments
Table 4-31 AFSR bit assignments
Table 4-12
4-31