Floating-Point Context Control Register; Fpccr Register Bit Assignments - ARM Cortex-M4 Generic User Manual

4.6.2

Floating-point Context Control Register

Bits Name
[31] ASPEN
[30] LSPEN
[29:9] -
[8] MONRDY
[7] -
[6] BFRDY
[5] MMRDY
[4] HFRDY
[3] THREAD
ARM DUI 0553A
ID121610
The FPCCR register sets or returns FPU control data. See the register summary in
floating-point system registers on page 4-48
31 30 29
LSPEN
ASPEN
Function
Enables
CONTROL<2>
hardware state preservation and restoration, for floating-point context, on exception entry and
exit.
0 = Disable
CONTROL<2>
1 = Enable
CONTROL<2>
0 = Disable automatic lazy state preservation for floating-point context.
1 = Enable automatic lazy state preservation for floating-point context.
Reserved.
0 = DebugMonitor is disabled or priority did not permit setting
stack frame was allocated.
1 = DebugMonitor is enabled and priority permits setting
frame was allocated.
Reserved.
0 = BusFault is disabled or priority did not permit setting the BusFault handler to the pending
state when the floating-point stack frame was allocated.
1 = BusFault is enabled and priority permitted setting the BusFault handler to the pending state
when the floating-point stack frame was allocated.
0 = MemManage is disabled or priority did not permit setting the MemManage handler to the
pending state when the floating-point stack frame was allocated.
1 = MemManage is enabled and priority permitted setting the MemManage handler to the
pending state when the floating-point stack frame was allocated.
0 = Priority did not permit setting the HardFault handler to the pending state when the
floating-point stack frame was allocated.
1 = Priority permitted setting the HardFault handler to the pending state when the floating-point
stack frame was allocated.
0 = Mode was not Thread Mode when the floating-point stack frame was allocated.
1 = Mode was Thread Mode when the floating-point stack frame was allocated.
Copyright © 2010 ARM. All rights reserved.
Non-Confidential
for its attributes. The bit assignments are:
Reserved
Table 4-51 FPCCR register bit assignments
setting on execution of a floating-point instruction. This results in automatic
setting on execution of a floating-point instruction.
setting on execution of a floating-point instruction.
Cortex-M4 Peripherals
Cortex-M4F
9 8 7 6 5 4 3
MONRDY
Reserved
BFRDY
MMRDY
HFRDY
THREAD
Reserved
USER
LSPACT
when the floating-point
MON_PEND
when the floating-point stack
MON_PEND
2 1 0
4-49