ARM Cortex r1p3 Technical Reference Manual

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-R4 and Cortex-R4F

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Revision: r1p3

Technical Reference Manual

ARM DDI 0363E (ID013010)

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Page 2: Change History
This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.
Page 3: Table Of Contents
Operating modes ... 2-4 Data types ... 2-5 Memory formats ... 2-6 Registers ... 2-7 Program status registers ... 2-10 Exceptions ... 2-16 Acceleration of execution environments ... 2-27 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access...
Page 4 Accessing RAMs using the AXI slave interface ... 9-24 About power control ... 10-2 Power management ... 10-3 Debug systems ... 11-2 About the debug unit ... 11-3 Debug register interface ... 11-5 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Contents...
Page 5 About the processor signal descriptions ... A-2 Global signals ... A-3 Configuration signals ... A-4 Interrupt signals, including VIC interface signals ... A-7 L2 interface signals ... A-8 TCM interface signals ... A-13 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Contents...
Page 6 Debug interface signals ... A-17 ETM interface signals ... A-19 Test signals ... A-20 MBIST signals ... A-21 Validation signals ... A-22 FPU signals ... A-23 ECC scheme selection guidelines ... B-2 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Contents...
Page 7: List Of Tables
Memory Model Feature Register 3 bit functions ... 4-25 Table 4-14 Instruction Set Attributes Register 0 bit functions ... 4-26 Table 4-15 Instruction Set Attributes Register 1 bit functions ... 4-28 ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access...
Page 8 Cache ECC error behavior ... 8-22 Table 8-4 Tag RAM bit descriptions, with parity ... 8-26 Table 8-5 Tag RAM bit descriptions, with ECC ... 8-26 ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access List of Tables viii...
Page 9 Debug memory-mapped registers ... 11-6 Table 11-4 External debug interface access permissions ... 11-9 Table 11-5 Terms used in register descriptions ... 11-10 ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access List of Tables...
Page 10 Data Processing Instruction cycle timing behavior if destination is not PC ... 14-7 Table 14-4 Data Processing instruction cycle timing behavior if destination is the PC ... 14-7 ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access List of Tables...
Page 11 ETM interface signals ... A-19 Table A-15 Test signals ... A-20 Table A-16 MBIST signals ... A-21 Table A-17 Validation signals ... A-22 ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access List of Tables...
Page 12 Table C-1 Differences between issue B and issue C ... C-1 Table C-2 Differences between issue C and issue D ... C-3 ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access List of Tables...
Page 13: List Of Figures
Processor Feature Register 1 format ... 4-19 Figure 4-14 Debug Feature Register 0 format ... 4-20 Figure 4-15 Memory Model Feature Register 0 format ... 4-22 ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access xiii...
Page 14 Sequential read operation performed with one RAM access ... 8-28 Figure 11-1 Typical debug system ... 11-2 Figure 11-2 Debug ID Register format ... 11-11 ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access List of Figures...
Page 15 ITMISCOUT Register bit assignments ... 13-8 Figure 13-3 ITMISCIN Register bit assignments ... 13-9 Figure 13-4 ITCTRL Register bit assignments ... 13-9 ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access List of Figures...
Page 16: Preface
This preface introduces the Cortex-R4 and Cortex-R4F Technical Reference Manual. It contains the following sections: • About this book on page xvii • Feedback on page xxi. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access...
Page 17: About This Book
Read this for a description of the functions of the Prefetch Unit (PFU), including dynamic branch prediction and the return stack. Read this for a description of the Performance Monitoring Unit (PMU) and the event bus. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Preface xvii...
Page 18 Highlights important notes, introduces special terminology, denotes internal cross-references, and citations. Highlights interface elements, such as menu names. Denotes signal names. Also used for terms in descriptive lists, where appropriate. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Preface xviii...
Page 19: Timing Diagrams
Denotes AXI read address channel signals. Denotes AXI write address channel signals. Denotes AXI write response channel signals. Denotes Advanced Peripheral Bus (APB) signals. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Preface Clock HIGH to LOW...
Page 20: Further Reading
• AMBA • AMBA 3 APB Protocol Specification (ARM IHI 0024) • ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition (ARM DDI 0406) • ARM PrimeCell (ARM DDI 0273) • Cortex-R4 and Cortex-R4F Integration Manual (ARM DII 0130) •...
Page 21: Feedback
Feedback ARM welcomes feedback on this product and its documentation. Feedback on this product If you have any comments or suggestions about this product, contact your supplier and give: • The product name. • The product revision or version. •...
Page 22 Redundant core comparison on page 1-19 • Test features on page 1-20 • Product documentation, design flow, and architecture on page 1-21 • Product revision information on page 1-24. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access...
Page 23: Chapter 1 Introduction
Error Checking and Correction (ECC) on all RAM blocks. single 64-bit master AXI interface 64-bit slave AXI interface to TCM RAM blocks and cache RAM blocks. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Introduction...
Page 24: About The Architecture
Cortex-R4F processor implements the VFPv3-D16 architecture. This includes the VFPv3 instruction set. The ARMv7-R architecture provides 32-bit ARM and 16-bit and 32-bit Thumb instruction sets, including a range of Single Instruction, Multiple-Data (SIMD) Digital Signal Processing (DSP) instructions that operate on 16-bit or 8-bit data values in 32-bit registers.
Page 25: Components Of The Processor
Tightly- Coupled Memory (TCM) interface instruction cache RAM L2 interface slave port AXI slave bus Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Debug Debug interface Data Load/Store Processing Unit Unit Memory Protection data cache...
Page 26: Load/Store Unit
It decodes and executes instructions, operating on data held in the registers in accordance with the ARM Architecture. Instructions are fed to the DPU from the PFU through a buffer. The DPU performs instructions that require data to be transferred to or from the memory system by interfacing to the LSU.
Page 27 Permissible TCM block sizes are: • • • • 16KB • 32KB • 64KB • 128KB • 256KB ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Introduction operations, and sequential instruction LDRD...
Page 28 AXI slave. Access to the TCM RAMs can be granted to any master, to only privileged masters, or completely disabled. Access to the cache RAMs can be separately controlled in a similar way. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Introduction...
Page 29 To get full access to the processor debug capability, you can access the debug register map through the APBv3 slave port. See Chapter 11 Debug for more information on debug. ARM DDI 0363E ID013010 Note Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Introduction...
Page 30: Exception Processing
VIC port The core has a dedicated port that enables an external interrupt controller, such as the ARM PrimeCell Vectored Interrupt Controller (VIC), to supply a vector address along with an Interrupt Request (IRQ) signal.
Page 31 ARM DDI 0363E ID013010 Return from exception using data from the stack. Change processor state, such as interrupt mask setting and clearing, and mode changes. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Introduction 1-10...
Page 32: External Interfaces Of The Processor
AMBA 3 APB Protocol Specification and the CoreSight Architecture Specification. 1.4.1 APB Debug interface AMBA APBv3 is used for debugging purposes. CoreSight is the ARM architecture for multi-processor trace and debug. CoreSight defines what debug and trace components are required and how they are connected.
Page 33: Power Management
TCM state, is stored to memory before entry into Dormant mode, and restored after exit. For more information on preparing the Cortex-R4 to support Dormant mode, contact ARM. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Introduction 1-12...
Page 34: Configurable Options
32-bit ECC error checking 64-bit ECC error checking 4KB, 8KB, 16KB, 32KB, 64KB, 128KB, 256KB, 512KB, 1MB, 2MB, 4MB, or 8MB Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Introduction Table 1-1 Configurable options Build-configuration or pin-configuration...
Page 35 Adjacent in memory Little-endian Big-endian 8 MPU regions 12 MPU regions Base address Base address configured Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Introduction Table 1-1 Configurable options (continued) Build-configuration or pin-configuration Build and pin Build...
Page 36: Table 1-2 Configurable Options At Reset
ATCM parity check enable BTCM parity check enable, for B0TCM and B1TCM independently ATCM ECC check enable BTCM ECC check enabled, for B0TCM and B1TCM together Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Table 1-1 Configurable options (continued) Build-configuration...
Page 37 Table 1-2 Configurable options at reset (continued) Options ATCM external error enable BTCM external error enable, for B0TCM and B1TCM independently ATCM load/store-64 enable BTCM load/store-64 enable Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Introduction Register ATCMECEN B0TCMECEN/...
Page 38: Execution Pipeline Stages
Mispredicted direct branches Exception flush and mispredicted indirect branches Figure 1-3 Cortex-R4 Issue and Execution pipeline stages Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Introduction Instruction fetch formatting Instruction stage branch...
Page 39: Figure 1-4 Cortex-R4F Issue And Execution Pipeline Stages
Second stage of data memory access. Floating point register read. First stage of floating point execution. Second stage of floating point execution. Floating point writeback. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Introduction Load/store pipeline Data...
Page 40: Redundant Core Comparison
DCCMOUT2[7:0] enable the comparison logic inside the processor to communicate with the rest of the system. ARM provides example comparison logic, but you can change this during implementation. If you are implementing a processor with dual-redundant cores, contact ARM for more information.
Page 41: Test Features
TCMs for the processor to execute. See Accessing RAMs using the AXI slave interface on page 9-24 for more information about how to access the RAMs using the AXI slave interface. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Introduction 1-20...
Page 42: Product Documentation, Design Flow, And Architecture
• the processes to sign off the configured RTL and final macrocell. The ARM product deliverables include reference scripts and information about using them to implement your design. Reference methodology documentation from your EDA tools vendor complements the CSG. The CSG is a confidential book that is only available to licensees.
Page 43 The behavior and encoding of the instructions that the processor can execute. • The modes and states that the processor can be in. • The various data and control registers that the processor must contain. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Introduction 1-22...
Page 44 System-on-Chip (SoC). It facilitates development of embedded processors with multiple peripherals. This is the IEEE Standard for Binary Floating Point Arithmetic. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Introduction 1-23...
Page 45: Product Revision Information
See Floating-Point System ID Register, FPSID on page 12-5. Note Floating point functionality is provided only with the Cortex-R4F processor. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Introduction 1-24...
Page 46: Table 1-3 Id Values For Different Product Versions
1.11.2 Architectural information The ARM Architecture includes a number of registers that identify the version of the architecture and some of the architectural features that a processor implements. Chapter 4 System Control Coprocessor describes the values that the processor implements for the fields in these registers.
Page 47: Chapter 2 Programmer's Model
• Acceleration of execution environments on page 2-27 • Unaligned and mixed-endian data access support on page 2-28 • Big-endian instruction support on page 2-29. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access...
Page 48: About The Programmer's Model
Reference Manual. This chapter describes some of the main features of the architecture but, for a complete description, see the ARM Architecture Reference Manual. This chapter also makes reference to older versions of the ARM architecture that the processor does not implement. These references are included to contrast the behavior of the Cortex-R4 processor with other processors you might have used that implement an older version of the architecture.
Page 49: Instruction Set States
2.2.1 Switching state The instruction set state of the processor can be switched between ARM state and Thumb state: • Using the that does not set flags, with the PC as the destination register. Switching state is described in the ARM Architecture Reference Manual.
Page 50: Operating Modes
Operating modes In each state there are seven modes of operation: • User (USR) mode is the usual mode for the execution of ARM or Thumb programs. It is used for executing most application programs. • Fast interrupt (FIQ) mode is entered on taking a fast interrupt.
Page 51: Data Types
Note to +2 -1, using two’s complement format. Note , or instructions to access 32-bit quantities if they are not LDRD STRD Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Programmer’s Model -1, using normal binary format.
Page 52: Memory Formats
ARM DDI 0363E ID013010 Memory Address A[31:0] Figure 2-1 Byte-invariant big-endian (BE-8) format Memory Address A[31:0] Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Programmer’s Model Register 24 23 16 15 msbyte lsbyte Register 24 23...
Page 53: Registers
2.6.1 The register set In the processor the same register set is used in both the ARM and Thumb states. Sixteen general registers and one or two status registers are accessible at any time. In Privileged modes, alternative mode-specific banked registers become available. Figure 2-3 on page 2-9 shows the registers that are available in each mode.
Page 54: Table 2-1 Register Mode Identifiers
Figure 2-3 on page 2-9 shows the register set, and those registers that are banked. ARM DDI 0363E ID013010 For more information, see the ARM Architecture Reference Manual. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Programmer’s Model...
Page 55: Figure 2-3 Register Organization
R15 (PC) R15 (PC) Program status registers CPSR CPSR SPSR_fiq SPSR_svc Note instruction to transfer a value from a low register, in Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Programmer’s Model Abort Undefined R13_abt R13_irq R13_und R14_abt...
Page 56: Program Status Registers
In ARM state, most instructions can execute conditionally on the state of the N, Z, C, and V bits. The exceptions are: •...
Page 57 In Thumb state, the processor can only execute the Branch instruction conditionally. Other instructions can be made conditional by placing them in the If-Then (IT) block. For more information about conditional execution in Thumb state, see the ARM Architecture Reference Manual.
Page 58: Table 2-2 Ge[3:0] Settings
For more information on the operation of the IT execution state bits, see the ARM Architecture Reference Manual. 2.7.4 The J bit The J bit in the CPSR returns 0 when read. You cannot use an 2.7.5 The DNM bits Software must not modify the Do Not Modify (DNM) bits.
Page 59 2.7.7 The E bit ARM and Thumb instructions are provided to set and clear the E bit. The E bit controls load/store endianness. See the ARM Architecture Reference Manual for information on where the E bit is used.
Page 60: Table 2-3 Psr Mode Bit Values
Note instruction must never modify, and so must only be written as a side-effect instruction tries to modify these bits, the results are Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Programmer’s Model Table 2-3 PSR mode bit values R0–R14, PC, CPSR...
Page 61 Programmer’s Model Bits in Figure 2-4 on page 2-10 that are in this category are A, I, F, and M[4:0]. ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 2-15 ID013010 Non-Confidential, Unrestricted Access...
Page 62: Exceptions
IA + 4 IA + 4 IA + 4 IA + 4 IA + 8 IA + 4 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Programmer’s Model Table 2-4 Exception entry and exit Previous state Notes...
Page 63 For more information about the IT instruction and Undefined instruction, and an example of the exception handler code, see the ARM Architecture Reference Manual.
Page 64: Interrupt Request
Forces the PC to fetch the next instruction from the reset vector address. Reverts to ARM state or Thumb state depending on the state of the TEINIT pin, and resumes execution. After reset, all register values except the PC and CPSR are indeterminate.
Page 65 LOW until the processor acknowledges the interrupt request from the software handler. Irrespective of whether exception entry is from ARM state or Thumb state, an FIQ handler returns from the interrupt by executing: SUBS PC, R14_fiq, #4 If Non-Maskable Fast Interrupts (NMFIs) are not enabled, you can mask FIQ exceptions by setting the CPSR.F bit to b1.
Page 66: Interrupt Controller
ARM for use in Cortex-R4 designs. You can use the VIC port to connect a PL192 VIC to the processor. See the ARM PrimeCell Vectored Interrupt Controller (PL192) Technical Reference Manual for more information about the PL192 VIC.
Page 67: Figure 2-5 Interrupt Entry Sequence
TRUE !(nFIQ||F) FALSE TRUE V==1 TRUE FALSE PC[31:0] = PC[31:0] = Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Programmer’s Model VE==1 FALSE TRUE Start handshake with VIC SPSR_irq = CPSR LR_irq = RA+4 CPSR[4:0] = IRQ mode...
Page 68: Prefetch Aborts
Link Register (r14_abt) to determine which instruction generated the abort, and the value in the Saved Program Status Register (SPSR_abt) to determine the state of the processor when the abort occurred. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Programmer’s Model 2-22...
Page 69 • fix the error and return to the instruction that was abandoned, to re-execute it ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Programmer’s Model instruction. Abort exceptions 2-23...
Page 70 SPSR are correct for the instruction following the SVC. This means that the SVC handler does not have to perform any special action to accommodate the IT instruction. For more information on the IT instruction, see the ARM Architecture Reference Manual.
Page 71: Breakpoint Instruction
When an instruction is encountered which is UNDEFINED, or is for the VFP when the VFP is not enabled, the processor takes the Undefined instruction exception. Software can use this mechanism to extend the ARM instruction set by emulating UNDEFINED coprocessor instructions. UNDEFINED exceptions also occur when a the value in Rm is zero, and the DZ bit in the System Control Register is set.
Page 72: Table 2-5 Configuration Of Exception Vector Address Locations
Undefined 0x04 Supervisor 0x08 Abort 0x0C Abort 0x10 0x18 0x1C Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Programmer’s Model Exception vector Value of V bit base location 0x00000000 1 (HIVECS) 0xFFFF0000 Table 2-6 Exception vectors A bit on entry...
Page 73: Acceleration Of Execution Environments
ARM DDI 0363E ID013010 Register Jazelle ID Jazelle main configuration Jazelle OS control Note Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Programmer’s Model software compatibility, three Jazelle ® Table 2-7 Jazelle register instruction summary Instruction Response Read as zero MRC p14, 7, <Rd>, c0, c0, 0...
Page 74: Unaligned And Mixed-Endian Data Access Support
The processor supports byte-invariant big-endianness BE-8 and little-endianness LE. The processor does not support word-invariant big-endianness BE-32. Bit [7] of c1, Control Register is always 0. For more information on unaligned and mixed-endian data access support, see the ARM Architecture Reference Manual. ARM DDI 0363E ID013010 Copyright ©...
Page 75: Big-Endian Instruction Support
If this facility is not present, the CFGIE pin is still reflected in the System Control Register but the instruction format is always little-endian. ARM DDI 0363E ID013010 Note Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Programmer’s Model 2-29...
Page 76: Chapter 3 Processor Initialization, Resets, And Clocking
It contains the following sections: • Initialization on page 3-2 • Resets on page 3-6 • Reset modes on page 3-7 • Clocking on page 3-9. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access...
Page 77: Initialization
The Current Program Status Register (CPSR) is given a known value on reset. This is described in the ARM Architecture Reference Manual. The reset values for the CP15 registers are described along with the registers in Chapter 4 System Control Coprocessor.
Page 78 The processor does not initialize the TCM RAMs. It is not essential to initialize all the memory attached to the TCM interface but ARM recommends that you do. In addition, you might want to preload instructions or data into the TCM for the main application to use. This section describes various ways that you can perform data preloading.
Page 79 TCMs through the AXI slave interface. This DAP is controlled from the debug host through a JTAG chain. Note instructions, enable strict-alignment-checking by setting the A-bit in the Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Processor Initialization, Resets, and Clocking...
Page 80 The processor does not halt if the nCPUHALT pin is asserted while the processor is running. ARM DDI 0363E ID013010 Note Note Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Processor Initialization, Resets, and Clocking...
Page 81: Resets
APB debug logic. See CP14 registers reset on page 11-23 for information. This signal stops the processor from fetching instructions after reset. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Processor Initialization, Resets, and Clocking...
Page 82: Reset Modes
Figure 3-1 shows the application of power-on reset. ARM recommends that you assert the reset signals for at least four CLKIN cycles to ensure correct reset behavior.
Page 83: Processor Reset
PFU starts fetching instructions from TCMs. When the processor has started fetching, nCPUHALT must not be asserted again except when the processor is reset. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Processor Initialization, Resets, and Clocking...
Page 84: Clocking
Standby mode. If you do, you must design the logic so that the TCM clock starts running within four cycles of STANDBYWFI going LOW. ARM DDI 0363E ID013010 CLKIN ACLKM ACLKENM Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Processor Initialization, Resets, and Clocking Figure 3-2 AXI interface clocking...
Page 85: Chapter 4 System Control Coprocessor
It contains the following sections: • About the system control coprocessor on page 4-2 • System control coprocessor registers on page 4-9. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access...
Page 86: About The System Control Coprocessor
Table 4-2 on page 4-9 lists the registers in the system control processor, in register order, and gives the reset value for each register. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor...
Page 87: Table 4-1 System Control Coprocessor Register Functions
Current Cache Size Identification Register on page 4-32 c0, Current Cache Level ID Register on page 4-34 c0, Cache Size Selection Register on page 4-35 Cache operations on page 4-54 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor...
Page 88: Figure 4-1 System Control And Configuration Registers
Opcode_2 {0, 1} {4–7} Read-only Read/write Figure 4-1 System control and configuration registers Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor Main ID Register Multiprocessor ID Register Processor Feature Registers 0, 1 Debug Feature Register 0...
Page 89: Figure 4-2 Mpu Control And Configuration Registers
Strongly Ordered. Opcode_1 Opcode_2 Read-only Read/write Figure 4-2 MPU control and configuration registers Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor MPU Type Register Data Fault Status Register Instruction Fault Status Register Auxilary Data Fault Status Register...
Page 90: Figure 4-3 Cache Control And Configuration Registers
Figure 4-3 Cache control and configuration registers Opcode_1 Opcode_2 Read-only Read/write Figure 4-4 TCM control and configuration registers Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor Cache Type Register Current Cache Size Identification Register Current Cache Level Identification Register Cache Size Selection Register Cache Operations Registers ‡...
Page 91: Figure 4-5 System Performance Monitor Registers
It can generate interrupts when the number of events reaches a given value. For more information on the programmer’s model of the performance counters see the ARM Architecture Reference Manual.
Page 92 You can only change the cache size to a size supported by the cache RAMs implemented in your design. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor...
Page 93: System Control Coprocessor Registers
CRn, Opcode_1, CRm, Opcode_2. For more information on using the system control coprocessor and the general method of how to access CP15 registers, see the ARM Architecture Reference Manual. 4.2.1 Register allocation...
Page 94 Undefined MPU Region Size and Enable Undefined MPU Region Access Control Undefined MPU Memory Region Number Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor Type Reset value Page Read-only page 4-32 Read-only page 4-34...
Page 95 Clean data cache line by physical address Clean data cache line by Set/Way Undefined Data Synchronization Barrier Data Memory Barrier Undefined Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor Type Reset value Page Write-only page 4-54 Write-only...
Page 96 Overflow Flag Status Software Increment Performance Counter Selection Undefined Cycle Count Event Select Performance Monitor Count Undefined Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor Type Reset value Page Write-only page 4-55 Write-only page 4-55...
Page 97 Enable Set nVAL IRQ Enable Clear nVAL FIQ Enable Clear nVAL Reset Enable Clear nVAL Debug Request Enable Clear Build Options 1 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor Type Reset value Page Read/write...
Page 98: Figure 4-7 Main Id Register Format
Correctable Fault Location Undefined Invalidate all data cache Undefined Cache Size Override Undefined 20 19 Implementor Variant Architecture Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor Type Reset value Read-only Read/write Unpredictable Write-only Write-only...
Page 99: Table 4-3 Main Id Register Bit Functions
CRn = c0, Opcode_1 = 0, CRm = c0, and an Opcode_2 28 27 24 23 DMinLine Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor Table 4-3 Main ID Register bit functions...
Page 100: Table 4-4 Cache Type Register Bit Functions
- eight words in an L1 instruction cache line. 19 18 16 15 Reserved BTCM Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor Table 4-4 Cache Type Register bit functions Reserved Figure 4-9 TCM Type Register format...
Page 101: Table 4-6 Mpu Type Register Bit Functions
The ATCM and BTCM fields in the TCM Type Register occupy the same space as the ITCM and DTCM fields as defined by the ARM Architecture. These fields, and the corresponding TCM interfaces, can be considered equivalent to those defined in the Architecture.
Page 102: Figure 4-11 Multiprocessor Id Register Format
Affinity Level 2 Figure 4-11 Multiprocessor ID Register format 16 15 Reserved Figure 4-12 Processor Feature Register 0 format Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor Affinity Level 1 Affinity Level 0 State3...
Page 103: Table 4-7 Processor Feature Register 0 Bit Functions
Microcontroller programmer’s model Security extension ARMv4 Programmer’s model Figure 4-13 Processor Feature Register 1 format Table 4-8 Processor Feature Register 1 bit functions Function SBZ. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor 12 11 4-19...
Page 104: Table 4-9 Debug Feature Register 0 Bit Functions
Indicates support for the trace debug model - memory mapped: , trace supported, memory mapped access. Indicates support for the trace debug model - coprocessor: , no support. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor 16 15...
Page 105: Table
Indicates the type of secure debug model that the processor supports: , no support. Indicates the type of applications processor debug model that the processor supports: , no support. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor 0x00000000...
Page 106: Table 4-10 Memory Model Feature Register 0 Bit Functions
Indicates support for Physical Memory System Architecture (PMSA). , the processor supports PMSAv7 (subsection support). Indicates support for Virtual Memory System Architecture (VMSA). , no support. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor 12 11...
Page 107: Table 4-11 Memory Model Feature Register 1 Bit Functions
Indicates support for L1 cache line maintenance operations by address, unified architecture. , no support. Indicates support for L1 cache line maintenance operations by address, Harvard architecture. , no support. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor 12 11 4-23...
Page 108: Table 4-12 Memory Model Feature Register 2 Bit Functions
Indicates support for background prefetch cache range operations, Harvard architecture. , no support. Indicates support for foreground prefetch cache range operations, Harvard architecture. , no support. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor 12 11 4-24...
Page 109: Table 4-13 Memory Model Feature Register 3 Bit Functions
Clean data cache by address • Clean and invalidate data cache by address • Invalidate instruction cache by address • Invalidate all instruction cache entries. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor 12 11 4-25...
Page 110: Table 4-14 Instruction Set Attributes Register 0 Bit Functions
CP15 registers and VFP. , no support. Indicates support for combined compare and branch instructions. , the processor supports combined compare and branch instructions, Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor 12 11 instructions.
Page 111: Table
Indicates support for atomic load and store instructions. , the processor supports 28 27 24 23 20 19 16 15 Figure 4-20 Instruction Set Attributes Register 1 format Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor , and SBFX UBFX SWPB...
Page 112: Table 4-15 Instruction Set Attributes Register 1 Bit Functions
, and T bit in PSRs • , and PC loads have BX behavior. • Data-processing instructions in the ARM instruction set with the PC as the destination and the S bit clear have BX-like behavior. Indicates support for immediate instructions. , the processor supports: •...
Page 113: Table 4-16 Instruction Set Attributes Register 2 Bit Functions
Indicates support for memory hint instructions. , the processor supports Indicates support for additional load and store instructions. , the processor supports LDRD STRD Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor 12 11 , and RBIT...
Page 114: Table 4-17 Instruction Set Attributes Register 3 Bit Functions
• LDREX STREX • LDREXB LDREXH LDREXD STREXB Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor 12 11 and various compatible hints in both the ARM low register ⇒ low register. , and STREXH...
Page 115: Table 4-18 Instruction Set Attributes Register 4 Bit Functions
[15:12] in the ISAR3 register. See c0, Instruction Set Attributes Register 3, ISAR3 on page 4-30 for more information. Indicates support for Barrier instructions. , the processor supports Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor ) instructions.
Page 116: Table
• register-controlled shift options. Indicates support for Unprivileged instructions. , the processor supports LDR{SB|B|SH|H}T Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor ) (formerly ) instructions. STR{B|H}T...
Page 117: Table 4-19 Current Cache Size Identification Register Bit Functions
Complete register encoding 0xF003E019 0xF007E019 0xF00FE019 0xF01FE019 0xF03FE019 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor 13 12 Associativity Function Indicates support available for write-through: 1 = write-through support available Indicates support available for write-back:...
Page 118: Table 4-21 Current Cache Level Id Register Bit Functions
CL 4 [8:6] CL 3 [5:3] CL 2 CL 1 CL 1 CL 1 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor 15 14 12 11 10 CL 5 CL 4 CL 3 CL 2...
Page 119: Table 4-22 Cache Size Selection Register Bit Functions
Table 4-22 Cache Size Selection Register bit functions Bits Field [31: 4] Reserved [3:1] Level Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor Level Function SBZ. Identifies which cache level to select. b000 = Level 1 cache This field is read only, writes are ignored.
Page 120: Table 4-23 System Control Register Bit Functions
Reserved SBZ. ARM DDI 0363E ID013010 SBO 1 Table 4-23 System Control Register bit functions Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor 3 2 1 0 Figure 4-27 System Control Register format 4-36...
Page 121: Table
1 = MPU enabled. If no MPU is implemented, the MPU has zero regions, this bit is SBZ. To use the System Control Register ARM recommends that you use a read-modify-write technique. To access the System Control Register, read or write CP15 with: MRC p15, 0, <Rd>, c1, c0, 0 ;...
Page 122: Table 4-24 Auxiliary Control Register Bit Functions
0 = Enabled. This is the reset value. 1 = Disabled. Case B1 dual issue control: 0 = Enabled. This is the reset value. 1 = Disabled. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor 3 2 1 0 ATCMECEN...
Page 123: Table
Fetch rate control disable: 0 = Normal fetch rate control operation. This is the reset value. 1 = Fetch rate control disabled. SBZ. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor defines the reset value.
Page 124: Table
Cache error control for cache parity and ECC errors. See Table 8-2 on page 8-21 and Table 8-3 on page 8-22 for details of how these bits are used. The reset value is b100. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor...
Page 125: Figure
MCR p15, 0, <Rd>, c1, c0, 1 ; Write Auxiliary Control Register ARM recommends that any instruction that changes bits [31:28] or [7] is followed by an instruction to ensure that the changes have taken effect before any dependent instructions are executed.
Page 126: Table 4-25 Secondary Auxiliary Control Register Bit Functions
1 = Disabled. Out-of-order Double Precision Floating Point instruction control. 0 = Enabled. This is the reset value. 1 = Disabled. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor 3 2 1 0 ATCMRMW...
Page 127: Table
1 = Propagate floating-point input denormal exception flag SBZ. Correction for internal ECC logic on BTCM ports. 0 = Enabled. This is the reset value. 1 = Disabled. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor to output FPIXC. FPSCR.IXC to output FPOFC.
Page 128: Table
MCR p15, 0, <Rd>, c15, c0, 0 ; Write Secondary Auxiliary Control Register ARM recommends that any instruction that changes bits [20:16] is followed by an instruction to ensure that the changes have taken effect before any dependent instructions are executed.
Page 129: Table 4-26 Coprocessor Access Register Bit Functions
Permission Precise External Abort Imprecise External Abort Precise Parity/ECC Error Imprecise Parity/ECC Error Lowest Debug Event Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor Table 4-27 Fault Status Register encodings [10,3:0] 0b00001 Valid 0b00000...
Page 130: Table 4-28 Data Fault Status Register Bit Functions
Figure 4-32 on page 4-47 shows the bit arrangement in the Instruction Fault Status Register. ARM DDI 0363E ID013010 Reserved Table 4-28 Data Fault Status Register bit functions Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor Domain Figure 4-31 Data Fault Status Register format...
Page 131: Table 4-29 Instruction Fault Status Register Bit Functions
Figure 4-33 on page 4-48 shows the bit arrangement in the auxiliary fault status registers. ARM DDI 0363E ID013010 Reserved Figure 4-32 Instruction Fault Status Register format Table 4-29 Instruction Fault Status Register bit functions Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor Domain Status Reserved...
Page 132: Table 4-30 Adfsr And Aifsr Bit Functions
1 = Recoverable error. This includes all correctable parity/ECC errors and recoverable TCM external errors. SBZ. This field returns the index value for the access giving the error. SBZ. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor 14 13 Index...
Page 133 TCM address space with the appropriate access permissions. You must define at least one of the regions in the MPU. An access to an undefined area of memory generates a background fault. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor...
Page 134: Table 4-31 Mpu Region Base Address Registers Bit Functions
Table 4-31 MPU Region Base Address Registers bit functions Bits Field Function [31:5] Base address Physical base address. Defines the base address of a region. [4:0] Reserved Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor Reserved 4-50...
Page 135: Table 4-32 Region Size Register Bit Functions
0 = Memory region disabled. Memory regions are disabled on reset. 1 = Memory region enabled. A memory region must be enabled before it is used. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor...
Page 136: Table 4-33 Mpu Region Access Control Register Bit Functions
Table 4-33 MPU Region Access Control Register bit functions Table 4-34 Access data permission bit encoding User permissions No access No access Read-only Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor 11 10 Reserved Description...
Page 137: Table 4-35 Mpu Memory Region Number Register Bit Functions
Read/write No access Read-only Reserved Figure 4-37 MPU Memory Region Number Register format Table 4-35 MPU Memory Region Number Register bit functions Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor Description Full access Reserved...
Page 138: Table
A point where instruction and data become unified and self-modifying code can function. instructions. Note , on the processor: ) instruction provides the Wait For Interrupt function. For more Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor 4-54...
Page 139: Invalidate And Clean Operations
This processor does not contain an address-based branch predictor array. Invalidate and clean operations The terms that describe the invalidate, clean, and prefetch operations are defined in the ARM Architecture Reference Manual. You can perform invalidate and clean operations on: •...
Page 140: Table 4-36 Functional Bits Of C7 For Set And Way
Table 4-36 Functional bits of c7 for Set and Way Table 4-37 Widths of the set field for L1 cache sizes Address Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor Figure 4-39 c7 format for Set and Way...
Page 141: Table 4-38 Functional Bits Of C7 For Address Format
To access the Data Synchronization Barrier operation, write CP15 with: MCR p15, 0, <Rd>, c7, c10, 4 ; Data Synchronization Barrier operation For more information about memory barriers, see the ARM Architecture Reference Manual. Data Memory Barrier operation The purpose of the Data Memory Barrier operation is to ensure that all outstanding explicit memory transactions complete before any following explicit memory transactions begin.
Page 142: Table 4-39 Btcm Region Register Bit Functions
Base address Table 4-39 BTCM Region Register bit functions b00110 = 32KB b00111 = 64KB b01000 = 128KB b01001 = 256KB Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor 12 11 Reserved Size Reserved...
Page 143: Table 4-40 Atcm Region Register Bit Functions
ID013010 Base address b00110 = 32KB b00111 = 64KB b01000 = 128KB b01001 = 256KB Note Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor 12 11 Reserved Size Reserved Figure 4-42 ATCM Region Registers Table 4-40 ATCM Region Register bit functions (RAMSize)-1):12] are ignored.
Page 144: Table 4-41 Slave Port Control Register Bit Functions
Enables or disables the AXI slave port for TCM accesses: 0 = Enables AXI slave port, reset value 1 = Disables AXI slave port. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor 2 1 0...
Page 145 The User read-only register can only be read in User mode, but can be read and written in Privileged modes. The Privileged-only register can be read and written in Privileged modes only. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor...
Page 146: Table 4-42 Nval Irq Enable Set Register Bit Functions
Cycle count overflow IRQ request enable Figure 4-44 nVAL IRQ Enable Set Register format Table 4-42 nVAL IRQ Enable Set Register bit functions Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor Performance monitor counter...
Page 147: Table 4-43 Nval Fiq Enable Set Register Bit Functions
Cycle count overflow FIQ request enable Figure 4-45 nVAL FIQ Enable Set Register format Table 4-43 nVAL FIQ Enable Set Register bit functions Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor Performance monitor counter...
Page 148: Table 4-44 Nval Reset Enable Set Register Bit Functions
Cycle count overflow reset request enable Figure 4-46 nVAL Reset Enable Set Register format Table 4-44 nVAL Reset Enable Set Register bit functions Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor Performance monitor counter...
Page 149: Table 4-45 Nval Debug Request Enable Set Register Bit Functions
Cycle count overflow debug request enable Figure 4-47 nVAL Debug Request Enable Set Register format Table 4-45 nVAL Debug Request Enable Set Register bit functions Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor Performance monitor counter...
Page 150: Table 4-46 Nval Irq Enable Clear Register Bit Functions
Table 4-46 nVAL IRQ Enable Clear Register bit functions Reserved Cycle count overflow FIQ request disable Figure 4-49 nVAL FIQ Enable Clear Register format Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor Performance monitor counter overflow IRQ request disables...
Page 151: Table 4-47 Nval Fiq Enable Clear Register Bit Functions
Performance monitor counter overflow reset request disable Figure 4-50 nVAL Reset Enable Clear Register format Table 4-48 nVAL Reset Enable Clear Register bit functions Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor Bits Field...
Page 152: Table 4-49 Nval Debug Request Enable Clear Register Bit Functions
Performance monitor counter overflow debug request disable Figure 4-51 nVAL Debug Request Enable Clear Register format Table 4-49 nVAL Debug Request Enable Clear Register bit functions Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor Bits...
Page 153: Table 4-50 Nval Cache Size Override Register
Defines the nVAL instruction cache size. See Table 4-51. Table 4-51 nVAL instruction and data cache size encodings Encoding b0000 b0001 b0011 b0111 b1111 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor Dcache Icache Instruction and data cache size 16kB 32kB...
Page 154: Figure 4-53 Correctable Fault Location Register - Cache
ID013010 Note Note 26 25 24 23 Side Reserved Reserved Figure 4-53 Correctable Fault Location Register - cache Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor 14 13 2 1 0 Index Reserved Type...
Page 155: Table 4-52 Correctable Fault Location Register - Cache
Indicates the address in the TCM where the error occurred. Reserved [1:0] Type Indicates the type of access that caused the error. 0b00 0b01 0b10 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor Address[22:3] Reserved = ATCM = BTCM = Instruction.
Page 156: Table 4-54 Build Options 1 Register
TCM_HI_INIT_ADDR Bits Field [31:12] TCM_HI_INIT_ADDR [11:0] Reserved Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor Reserved Figure 4-55 Build Options 1 Register format Table 4-54 Build Options 1 Register Function Default high address for the TCM.
Page 157: Table 4-55 Build Options 2 Register
00 = no error scheme 01 = 8-bit parity logic 10 = 32-bit error detection and correction 11 = 64-bit error detection and correction. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor 14 13 12 11...
Page 158 01 = 8-bit parity error detection 11 = 64-bit error detection and correction. If the processor does not contain an i-cache, these bits are set to 00. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor...
Page 159 Indicates whether the processor contains AXI bus parity logic. 0 = processor does not contain AXI bus parity logic 1 = processor contains AXI bus parity logic. Undefined. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access System Control Coprocessor 4-75...
Page 160: About The Prefetch Unit
It contains the following sections: • About the prefetch unit on page 5-2 • Branch prediction on page 5-3 • Return stack on page 5-5. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access...
Page 161: About The Prefetch Unit
The PFU fetches instructions from the memory system under the control of the DPU, and the internal coprocessors CP14 and CP15. In ARM state the memory system can supply up to two instructions per cycle. In Thumb state the memory system can supply up to four instructions per cycle.
Page 162: Branch Prediction
, and loads to the PC from an address derived from R13 from R0-R14. Note Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Prefetch Unit immediate, where the target address is a ), instructions which write to...
Page 163 The DPU resolves branches that the dynamic branch predictor predicts at the Wr-stage of the pipeline, see Figure 1-3 on page 1-17. A misprediction causes the PFU to flush the pipeline and fetch the correct instruction stream. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Prefetch Unit...
Page 164: Return Stack
When the return stack detects a taken return instruction, the PFU issues an instruction fetch from the location at the top of the return stack, and pops the return stack. The instructions that the PFU recognizes as procedure returns are, in both the ARM and Thumb instruction sets: •...
Page 165: Chapter 6 Events And Performance Monitor
About the events on page 6-2 • About the PMU on page 6-6 • Performance monitoring registers on page 6-7 • Event bus interface on page 6-19. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access...
Page 166: About The Events
This event occurs on each exception taken. ARM DDI 0363E ID013010 , or other operations. CP15 cache maintenance operations do not Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Events and Performance Monitor Table 6-1 Event bus interface bit functions...
Page 167: Table
BX Rm; LDM PC does not generate this event, because it is not predicted as a return. , Strongly Ordered memory access, or similar events. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Events and Performance Monitor...
Page 168: Table
B1TCM single-bit ECC error. ARM DDI 0363E ID013010 Table 6-1 Event bus interface bit functions (continued) , executed. SDIV UDIV 0x04 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Events and Performance Monitor Event CFLR Ref. update Value...
Page 169: Table
This event is only generated for by revisions r1p2 and later of the processor. ARM DDI 0363E ID013010 Table 6-1 Event bus interface bit functions (continued) Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Events and Performance Monitor Event CFLR Ref.
Page 170: About The Pmu
DP bit of the PMNC register is set. See c9, Performance Monitor Control Register on page 6-7. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Events and Performance Monitor...
Page 171: Performance Monitoring Registers
ID013010 24 23 IDCODE = ARM = Cortex-R4 = three counters implemented Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Events and Performance Monitor 16 15 4 3 2 1 0 Reserved Figure 6-1 PMNC Register format...
Page 172: Figure
Performance Monitor Control Register on page 6-7. Figure 6-2 on page 6-9 shows the bit arrangement for the CNTENS Register. ARM DDI 0363E ID013010 Table 6-2 PMNC Register bit functions (continued) Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Events and Performance Monitor...
Page 173: Table 6-3 Cntens Register Bit Functions
Figure 6-3 on page 6-10 shows the bit arrangement for the CNTENC Register. ARM DDI 0363E ID013010 Reserved Cycle count enable Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Events and Performance Monitor Performance monitor counter enables...
Page 174: Table 6-4 Cntenc Register Bit Functions
Figure 6-4 on page 6-11 shows the bit arrangement for the FLAG Register. ARM DDI 0363E ID013010 Reserved Cycle count disable Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Events and Performance Monitor Performance monitor counter disables...
Page 175: Table 6-5 Overflow Flag Status Register Bit Functions
Cycle counter overflow [30:3] Reserved Caution , software count, in the Event Select Register, see c9, Event 0x00 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Events and Performance Monitor 3 2 1 0 Performance monitor counters overflow flags...
Page 176: Table 6-6 Swincr Register Bit Functions
Figure 6-6 shows the bit arrangement for the PMNXSEL Register. ARM DDI 0363E ID013010 Reserved Bits [31:3] Reserved Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Events and Performance Monitor the result is Unpredictable. 0x00 3 2 1 0 Performance monitor counters...
Page 177: Table 6-7 Performance Counter Selection Register Bit Functions
Figure 6-7 on page 6-14 shows the bit arrangement for the EVTSELx Register. ARM DDI 0363E ID013010 Table 6-7 Performance Counter Selection Register bit functions Bits [31:5] [4:0] Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Events and Performance Monitor Field Function Reserved RAZ on reads, SBZP on writes...
Page 178: Table 6-8 Evtselx Register Bit Functions
[7:0] Event number selected, see Table 6-1 on page 6-2 for values. The reset value of this field is Unpredictable. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Events and Performance Monitor Figure 6-7 EVTSELx Register format...
Page 179: Table 6-9 Useren Register Bit Functions
User mode access to performance monitor and validation registers: 0 = Disabled. This is the reset value. 1 = Enabled. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Events and Performance Monitor Figure 6-8 USEREN Register format...
Page 180: Table 6-10 Intens Register Bit Functions
Note Reserved Cycle count overflow interrupt enable Bits [31] [30:3] Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Events and Performance Monitor 3 2 1 0 Performance monitor counter overflow interrupt enables Figure 6-9 INTENS Register format...
Page 181: Table 6-11 Intenc Register Bit Functions
If this unit generates an interrupt, the processor asserts the pin nPMUIRQ. You can route this pin to an external interrupt controller for prioritization and masking. This is the only mechanism that signals this interrupt to the processor. ARM expects that the Performance Monitor interrupt request signal, nPMUIRQ, connects to a system interrupt controller. 6.3.12...
Page 182 MRC p15, 0, <Rd>, c9, c14, 2 ; Read INTENC Register MCR p15, 0, <Rd>, c9, c14, 2 ; Write INTENC Register ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Events and Performance Monitor 6-18...
Page 183: Table
ETM. These inputs can alternatively be used for composite events generated external to the processor. ARM DDI 0363E ID013010 Note Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Events and Performance Monitor 6-19...
Page 184: Chapter 7 Memory Protection Unit
Region attributes on page 7-9 • MPU interaction with memory system on page 7-11 • MPU faults on page 7-12 • MPU software-accessible registers on page 7-13. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access...
Page 185: About The Mpu
About the MPU The MPU works with the L1 memory system to control accesses to and from L1 and external memory. For a full architectural description of the MPU, see the ARM Architecture Reference Manual. The MPU enables you to partition memory into regions and set individual protection attributes for each region.
Page 186: Table
SBZ/UNP for regions of less than 256 bytes in size. ARM DDI 0363E ID013010 Note Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Memory Protection Unit...
Page 187: Figure
To ensure correct operation, only a memory region that has permission for data read access can execute instructions. For more information, see the ARM Architecture Reference Manual. For information about how to program access permissions, see Table 4-34 on page 4-52.
Page 188: Figure 7-1 Overlapping Memory Regions
If the current process overflows the stack it uses, a write access by the processor to the disabled subregion causes the MPU to raise a background fault. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Memory Protection Unit Region 2...
Page 189: Figure 7-3 Overlapping Subregion Of Memory
Access permissions for an address in a TCM region are preserved from the MPU region that the address also belongs to. For more information, see About the TCMs on page 8-13. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Memory Protection Unit Guard region...
Page 190: Memory Types
Memory types The ARM Architecture defines a set of memory types with characteristics that are suited to particular devices. There are three mutually exclusive memory type attributes: • Strongly Ordered • Device • Normal. MPU memory regions can each be assigned a memory type attribute. Table 7-2 shows a summary of the memory types.
Page 191 Use Device memory type for appropriate memory regions, typically peripherals, and only use Strongly Ordered memory type for memory regions where it is essential. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Memory Protection Unit...
Page 192: Region Attributes
Outer and Inner write-back, no write-allocate. Outer and Inner Non-cacheable. Reserved. Outer and Inner write-back, write-allocate. Non-shareable Device. Reserved. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Memory Protection Unit Table 7-3 TEX[2:0], C, and B encodings Memory Type Shareable?
Page 193: Table 7-4 Inner And Outer Cache Policy Encoding
• the Outer attributes are indicated on the and A*CACHEM signals. For the encodings, see Table 9-2 on page 9-5. For more information on region attributes, see the ARM Architecture Reference Manual. ARM DDI 0363E ID013010 Table 7-3 TEX[2:0], C, and B encodings (continued) Description Reserved.
Page 194: Mpu Interaction With Memory System
ARM DDI 0363E ID013010 ; read CP15 register 1 ; enable MPU ; read CP15 register 1 ; disable MPU Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Memory Protection Unit instructions to ensure that all subsequent 7-11...
Page 195: Mpu Faults
A-bit in the System Control Register. See c1, System Control Register on page 4-35. ARM DDI 0363E ID013010 , require strict alignment. See the ARM Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Memory Protection Unit 7-12...
Page 196: Figure
When the MPU is not present, the c6, MPU memory region programming registers on page 4-49 read as zero and ignore writes in Privileged mode. No Undefined instruction exceptions are taken. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Memory Protection Unit 7-13...
Page 197: Chapter 8 Level One Memory System
• Internal exclusive monitor on page 8-34 • Memory types and L1 memory system behavior on page 8-35 • Error detection events on page 8-36. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access...
Page 198: Figure
The L1 memory system includes a monitor for exclusive accesses. Exclusive load and store instructions can be used, for example, provide inter-process or inter-processor synchronization and semaphores. See the ARM Architecture Reference Manual for more details. The monitor can handle some exclusive monitoring internally to the processor.
Page 199: Figure 8-1 L1 Memory System Block Diagram
Prefetch Unit Load Store Unit Protection Unit (PFU) (LSU) (MPU) AXI slave Data Processing Unit (DPU) AXI bus Figure 8-1 L1 memory system block diagram ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. ID013010 Non-Confidential, Unrestricted Access...
Page 200: About The Error Detection And Correction Schemes
Odd or even parity can be used, and this can be pin-configured during integration. ARM DDI 0363E ID013010 Figure 8-2 Error detection and correction schemes Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level One Memory System Parity: one error per byte detected...
Page 201: Error Checking And Correction
The processor contains features that enable it to recover from some hard errors. If you are implementing the processor and require these features, contact ARM to discuss the features and your requirements.
Page 202: Table
Note Because RAM errors generally occur infrequently, the extra cycles required to perform correct-and-retry do not have a significant impact on average performance. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level One Memory System...
Page 203: Table
TCM, and is Non-cacheable, or has generated a cache-miss, the AXI transactions for that access is not performed. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level One Memory System...
Page 204: Table
A retry request from the TCM port is considered to be a recoverable error. All correctable ECC faults are also considered to be recoverable. ARM DDI 0363E ID013010 Note Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level One Memory System...
Page 205 Note When a prefetch abort has occurred, ARM recommends that you do not use the link register value for determining the aborting address, because 32-bit Thumb instructions do not have to be word aligned and can cause an abort on either halfword.
Page 206: Table
Because the DFAR is not updated on imprecise aborts, imprecise aborts cannot normally be located, except when the error occurred in the cache. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level One Memory System...
Page 207: Correctable Errors
Load from cache Load/store from/to TCM Load/store from/to TCM Store to cache or cache maintenance operation Store to TCM Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level One Memory System Table 8-1 Types of aborts Source...
Page 208 Instead, the sticky precise abort flag in the DSCR is set. See CP14 c1, Debug Status and Control Register on page 11-14. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level One Memory System 8-12...
Page 209: Table
XN permissions are applied to TCM accesses to that address. None of the other device or strongly-ordered behaviors apply to an address in a TCM region. ARM DDI 0363E ID013010 Note Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level One Memory System 8-13...
Page 210 ARM DDI 0363E ID013010 Bit [3] of the address The most significant bit of the BTCM interface address. This depends on the size of the BTCM. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level One Memory System 8-14...
Page 211: Table
PFU, with the AXI slave having lowest priority. When a higher-priority device is accessing a TCM port, an access from a lower-priority device must stall. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level One Memory System 8-15...
Page 212 ERRENRAM input as required. ARM DDI 0363E ID013010 . In both cases, the initial base address of the other TCM is Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level One Memory System . If...
Page 213 For more information on the AXI slave interface, see AXI slave interface on page 9-20. ARM DDI 0363E ID013010 Note Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level One Memory System 8-17...
Page 214: About The Caches
See Cache error detection and correction on page 8-20 for more information. For more information on the general rules about memory attributes and behavior, see the ARM Architecture Reference Manual.
Page 215 Strongly Ordered memory an exclusive load or store to Shared memory to Non-cacheable memory. SWPB Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level One Memory System 8-19...
Page 216 The dirty RAM includes four bits of ECC to cover the dirty bit and the two outer attributes bits. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level One Memory System 8-20...
Page 217: Table 8-2 Cache Parity Error Behavior
The processor includes features that enable it to detect some address decoder faults. If you are implementing the processor and require these features, contact ARM to discuss the features and your requirements.
Page 218: Table 8-3 Cache Ecc Error Behavior
Enable hardware recovery, do not generate aborts on ECC errors Force write-through, enable hardware recovery, do not generate aborts on ECC errors Reserved Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level One Memory System Table 8-3 Cache ECC error behavior...
Page 219 Invalidate all data cache on page 8-24 • Invalidate instruction cache by address on page 8-24 • Invalidate data cache by address on page 8-24 ARM DDI 0363E ID013010 Note Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level One Memory System 8-23...
Page 220 Any uncorrectable errors cause an imprecise abort. An imprecise abort can also be raised on a correctable error if aborts on RAM errors are enabled in the Auxiliary Control Register. ARM DDI 0363E ID013010 Note Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level One Memory System 8-24...
Page 221 WSTRBM AXI signal deasserted. If there is a correctable error, the line has the error corrected inline before it is written back to memory. ARM DDI 0363E ID013010 Note Note Note Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level One Memory System 8-25...
Page 222: Table 8-4 Tag Ram Bit Descriptions, With Parity
Table 8-4 Tag RAM bit descriptions, with parity Table 8-5 Tag RAM bit descriptions, with ECC Table 8-6 Tag RAM bit descriptions, no parity or ECC Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level One Memory System...
Page 223: Table 8-7 Cache Sizes And Tag Ram Organization
01 = WB, WA 10 = WT 11 = WB, no WA 00 = Non-cacheable. Dirty bit Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level One Memory System Cache size Tag RAM organization 4 banks 23 bits 32 lines...
Page 224: Figure 8-3 Nonsequential Read Operation Performed With One Ram Access
Word 1 Word 0 Bank 1 Bank 2 Bank 3 Figure 8-4 Sequential read operation performed with one RAM access Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level One Memory System Way 3 Way 0 Way 3...
Page 225: Table 8-9 Instruction Cache Data Ram Sizes, No Parity Or Ecc
8KB, 4 2KB ways 16KB, 4 4KB ways 32KB, 4 8KB ways 64KB, 4 16KB ways Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level One Memory System Data RAMs 4 banks 64 bits 128 lines or...
Page 226: Table 8-13 Data Cache Ram Bits, With Parity
4KB, 4 1KB ways 8KB, 4 2KB ways 16KB, 4 4KB ways 32KB, 4 8KB ways 64KB, 4 16KB ways Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level One Memory System Data RAMs 8 banks 36 bits 128 lines...
Page 227: Table 8-15 Data Cache Data Ram Sizes With Ecc
ARM DDI 0363E ID013010 Table 8-15 Data cache data RAM sizes with ECC ; instruction cache enable ; data cache enable Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level One Memory System Cache size Data RAMs...
Page 228 ; Read System Control Register configuration data ; instruction cache enable ; disabled instruction cache ; Disable data cache bit ; Disable instruction cache bit Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level One Memory System 8-32...
Page 229 MCR p15, 0, r0, c1, c0, 0 ; Write System Control Register ARM DDI 0363E ID013010 ; Enable data cache bit ; Enable instruction cache bit Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level One Memory System 8-33...
Page 230: Internal Exclusive Monitor
By adding an external exclusive monitor, you can also use these instructions in the L2 memory system to construct semaphores and ensure synchronization between different processors. See the ARM Architecture Reference Manual for more information about how these instructions work.
Page 231: Memory Types And L1 Memory System Behavior
ARM DDI 0363E ID013010 instructions to Cacheable memory are not marked SWPB Table 8-17 Memory types and associated behavior Cacheable Merging Restartable Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level One Memory System Internal Locked exclusives swaps Partially...
Page 232: Error Detection Events
See Correctable Fault Location Register on page 4-70 for more information. Every correctable error that is recorded in the CFLR also ARM DDI 0363E ID013010 Note Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level One Memory System 8-36...
Page 233: Table
CLFR does not record whether the error occurred in the data RAM or tag/dirty RAM. This distinction is only made by the events. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level One Memory System 8-37...
Page 234: Chapter 9 Level Two Interface
AXI slave interface on page 9-20 • Enabling or disabling AXI slave accesses on page 9-23 • Accessing RAMs using the AXI slave interface on page 9-24. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access...
Page 235: About The L2 Interface
RAMs. You can use the AXI slave interface for DMA access into and out of the TCMs or to perform software test of the TCMs and cache RAMs. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level Two Interface...
Page 236: Axi Master Interface
Made up of five linefills on the data side, one NC read on the data side, and one linefill or NC read on the instruction side. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level Two Interface...
Page 237 ID can be sent when the address or data channel is released. For example, the new address can be sent with the same ID, before the target accepts the data of the first write. Note Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level Two Interface...
Page 238: Memory Attributes
Cacheable, write-back, read- and write-allocate, Non-shared b11111 Cacheable, write-back, read- and write-allocate, shared a. All encodings not shown in the table are reserved. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level Two Interface Meaning Strongly Ordered...
Page 239 AXI transfer. This means that the access examples given in this chapter never show unaligned accesses to Device or Strongly Ordered memory. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level Two Interface...
Page 240: Table
Non-cacheable or write-through writes on page 9-15 • AXI transaction splitting on page 9-16 • Normal write merging on page 9-17. ARM DDI 0363E ID013010 Note Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level Two Interface...
Page 241: Table 9-4 Non-Cacheable Ldrb
Address[2:0] ARADDRM (byte 0) 0x00 (byte 1) 0x01 (byte 2) 0x02 (byte 3) 0x03 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level Two Interface Table 9-4 Non-cacheable LDRB ARBURSTM ARSIZEM ARLENM Incr 8-bit 1 data transfer...
Page 242: Table 9-5 Ldrh From Strongly Ordered Or Device Memory
Table 9-6 LDR or LDM1 from Strongly Ordered or Device memory Address[2:0] ARADDRM (word 0) 0x00 (word 1) 0x04 Note Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level Two Interface Table 9-4 Non-cacheable LDRB (continued) ARBURSTM ARSIZEM ARLENM Incr...
Page 243: Table 9-7 Ldm5, Strongly Ordered Or Device Memory
0x04 0x04 (word 2) 0x08 0x08 (word 3) 0x0C 0x0C Note Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level Two Interface 5) in Strongly Ordered or Device memory. ARBURSTM ARSIZEM ARLENM Incr 32-bit 5 data transfers...
Page 244: Table 9-8 Strb To Strongly Ordered Or Device Memory
Table 9-9 STRH to Strongly Ordered or Device memory AWADDRM AWBURSTM Incr 0x00 Incr 0x02 Incr 0x04 Incr 0x06 Note Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level Two Interface AWSIZEM AWLENM WSTRBM 8-bit 1 data transfer b00000001 8-bit 1 data transfer b00000010...
Page 245: Stm7 To Strongly Ordered Or Device Memory To Word 0 Or 1
Table 9-11 STM7 to Strongly Ordered or Device memory to word 0 or 1 AWADDRM AWBURSTM Incr 0x00 Incr 0x04 Note Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level Two Interface 1) over the AXI master port to Strongly AWSIZEM AWLENM 32-bit 1 data transfer...
Page 246: Table 9-12 Linefill Behavior On The Axi Interface
Table 9-14 LDRH from Non-cacheable Normal memory Address[2:0] ARADDRM (byte 0) 0x00 (byte 1) 0x00 (byte 2) 0x00 (byte 3) 0x03 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level Two Interface ARBURSTM ARSIZEM ARLENM Wrap 64-bit 4 data transfers Wrap 64-bit...
Page 247: Table 9-15 Ldr Or Ldm1 From Non-Cacheable Normal Memory
(word 3) 0x0C 0x0C (word 4) 0x10 0x10 0x00 (word 5) 0x14 0x14 0x00 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level Two Interface ARBURSTM ARSIZEM ARLENM Incr 16-bit 1 data transfer Incr 32-bit 1 data transfer...
Page 248: Table 9-17 Strh To Cacheable Write-Through Or Non-Cacheable Normal Memory
Incr 0x03 Incr 0x04 Incr 0x05 Incr 0x06 Incr 0x07 Incr 0x08 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level Two Interface ARBURSTM ARSIZEM ARLENM Incr 64-bit 1 data transfer Incr 64-bit 2 data transfers Incr...
Page 249: Table 9-18 Str Or Stm1 To Cacheable Write-Through Or Non-Cacheable Normal Memory
LDMIA R10, {R0-R5} R10 = 0x1008 Table 9-19 AXI transaction splitting, all six words in same cache line ARADDRM 0x1008 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level Two Interface 1, to Normal memory through AWSIZEM...
Page 250: Table 9-20 Axi Transaction Splitting, Data In Two Cache Lines
Non-cacheable Normal memory that crosses a cache line boundary. AWADDRM AWBURSTM (byte 31) Incr 0x1F Incr 0x00 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level Two Interface , the interface might generate one burst of two ARBURSTM ARSIZEM ARLENM Incr...
Page 251: Table 9-23 Axi Transactions For Strongly Ordered Or Device Type Memory
0x401D AWADDRM AWBURSTM Incr 0x4000 STRB instruction has not occurred, because it was overwritten by instruction. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level Two Interface Example 9-1 Write merging AWSIZEM AWLENM WSTRBM 16-bit 1 data transfer...
Page 252: Table
AXI write transactions occur until the cache line is evicted and performs a write-back transaction. See Cache line write-back (eviction) on page 9-13. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level Two Interface 9-19...
Page 253: Axi Slave Interface
RAMs is accessed within the caches. The AXI access is given a SLVERR error response when access to nonexistent cache RAM is indicated. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level Two Interface 9-20...
Page 254: Table
See Auxiliary Control Registers on page 4-38. The AXI access is given a SLVERR error response when access is not permitted. ARM DDI 0363E ID013010 Note Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level Two Interface 9-21...
Page 255: Table 9-25 Axi Slave Interface Attributes
All write data must be presented to the AXI slave interface in order The AXI slave interface returns all read data in order, even if the bursts have different IDs Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level Two Interface...
Page 256: Enabling Or Disabling Axi Slave Accesses
Fetch from cached memory ARM DDI 0363E ID013010 ; Read Auxiliary Control Register ; disabled AXI slave accesses to the cache RAMs Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level Two Interface instruction must flush the pipeline so 9-23...
Page 257: Accessing Rams Using The Axi Slave Interface
Because AWUSERS and AWADDRS work in the same way as ARUSERS and ARADDRS, the following sections only describe ARUSERS and ARADDRS. ARM DDI 0363E ID013010 Note Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level Two Interface Table 9-26 RAM region decode AxUSERS bit...
Page 258: Table 9-27 Tcm Chip-Select Decode
ARADDRS[22:MSB+1] are non-zero. ARM DDI 0363E ID013010 ARADDRS[3] ARADDRS[MSB] Table 9-28 MSB bit for the different TCM RAM sizes Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level Two Interface Table 9-27 TCM chip-select decode SLBTCMSB RAM selected...
Page 259: Table 9-29 Cache Ram Chip-Select Decode
0010 1000 0011 1000 ARADDRS[22:21] != 00 Table 9-30 Cache tag/valid RAM bank/address decode Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level Two Interface Table 9-29 Cache RAM chip-select decode RAM selected Instruction cache data RAM...
Page 260: Table 9-32 Data Format, Instruction Cache And Data Cache, No Parity And No Ecc
0010 0100 0100 1000 1000 Note Table 9-32 Data format, instruction cache and data cache, no parity and no ECC Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level Two Interface Inputs RAM bank Cache selected ARADDRS[18:15]...
Page 261: Table 9-33 Data Format, Instruction Cache And Data Cache, With Parity
If accessing bits [15:0] of the data, bits [19:16] hold the lower half of the ECC code. If accessing bits [47:32] of the data, bits [19:16] hold the upper half of the ECC code. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access...
Page 262: Table 9-36 Tag Register Format For Reads, No Parity Or Ecc
Table 9-36 Tag register format for reads, no parity or ECC Table 9-37 Tag register format for reads, with parity Table 9-38 Tag register format for reads, with ECC Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level Two Interface...
Page 263: Table 9-39 Tag Register Format For Writes, No Parity Or Ecc
Table 9-39 Tag register format for writes, no parity or ECC Table 9-40 Tag register format for writes, with parity Table 9-41 Tag register format for writes, with ECC Note Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level Two Interface Data bit...
Page 264: Table 9-42 Dirty Register Format, With Parity Or With No Error Scheme
RAM is not used and does not require parity protection. ARM DDI 0363E ID013010 Table 9-42 Dirty register format, with parity or with no error scheme Note Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level Two Interface Data bit Description...
Page 265 RAM accesses the same physical location accesses are aliased and no errors are generated. ARM DDI 0363E ID013010 Table 9-43 Dirty register format, with ECC (continued) Note Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Level Two Interface Data bit Description [14:11]...
Page 266: About Power Control
This chapter describes the processor power control functions. It contains the following sections: • About power control on page 10-2 • Power management on page 10-3. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access 10-1...
Page 267: About Power Control
In the processor, extensive use is also made of gated clocks and gates to disable inputs to unused functional blocks. Only the logic actively in use to perform a calculation consumes any dynamic power. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Power Control 10-2...
Page 268: Power Management
RAMs, is powered down. In dormant mode, the processor state, apart from the cache and TCM state, is stored to memory before entry into this mode, and restored after exit. For more information on how to implement and use dormant mode in your design, contact ARM. 10.2.4...
Page 269 The STANDBYWFI signal can also signal that the processor is ready to have its power state changed. STANDBYWFI is asserted in response to a ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Power Control instruction. The STANDBYWFI signal is operation.
Page 270: Debug
External debug interface on page 11-51 • Using the debug functionality on page 11-54 • Debugging systems with energy management capabilities on page 11-71. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access 11-1...
Page 271: Debug Systems
Host computer running RealView Debugger host Protocol converter Debugger. The debug host enables you to issue high-level commands such ™ Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access For example, RealView ICE Debug Development system containing target...
Page 272: Table
The state of the processor is preserved in the same manner as all ARM exceptions. The monitor target communicates with the debugger to access processor and coprocessor state, and to access memory contents and peripherals. Monitor debug-mode requires a debug monitor program to interface between the debug hardware and the software debugger.
Page 273 Debug Communication Channel (DCC), see Debug communications channel on page 11-55 • all other state information associated with the debug unit. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Debug 11-4...
Page 274: Debug Register Interface
You can access the processor debug register map using the APB slave port. This is the only way to get full access to the processor debug capability. ARM recommends that if your system requires the processor to access its own debug registers, you choose a system interconnect structure that enables the processor to access the APB slave port by executing load and stores to an appropriate area of physical memory.
Page 275: Table 11-2 Cp14 Debug Registers Summary
Vector Catch Register on page 11-19 Not implemented in this processor. Reads as zero. DSCCR Debug State Cache Control Register on page 11-21. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Table 11-2 CP14 debug registers summary Table 11-3 Debug memory-mapped registers...
Page 276 11-30 PRSR Device Power-down and Reset Status Register on page 11-30 Processor ID Registers on page 11-32 Chapter 13 Integration Test Registers Management registers on page 11-32 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Debug 11-7...
Page 277: Figure
You can place additional restrictions on memory transactions that are permitted to access the APB port. However, ARM does not recommend this. Locks permission You can lock the APB slave port so that access to some debug registers is restricted. ARM Architecture v7 defines two locks: Software lock...
Page 278: Table 11-4 External Debug Interface Access Permissions
The processor does not support OS Lock. Note Table 11-4 External debug interface access permissions DRCR, PRCR, PRSR Other Debug registers NPOSS NPOSS Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Registers Other registers NPOSS NPOSS Debug...
Page 279: Debug Register Descriptions
Debug Self Address Offset Register Reserved Debug Status and Control Register Reserved Reserved Data Transfer Register Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Table 11-6 CP14 debug register map Abbreviation Reference DIDR CP14 c0, Debug ID...
Page 280: Table 11-7 Debug Id Register Functions
Implementation-defined variant number. See Product revision information on page 1-24 for details of the value of this field. Implementation-defined revision number. See Product revision information on page 1-24 for details of the value of this field. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Debug Reserved...
Page 281: Table 11-8 Debug Rom Address Register Functions
Indicates that the ROM address is valid. Reads b11 if DBGROMADDRV is set to 1, otherwise reads b00. DBGROMADDRV must be set to 1 if DBGROMADDR[31:12] is set to a valid value. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Debug multiprocessor trace and debug ™...
Page 282: Table 11-9 Debug Self Address Offset Register Functions
Reads b11 if DBGSELFADDRV is set to 1, otherwise reads b00. DBGSELFADDRV must be set to 1 if DBGSELFADDR[31:12] is set to a valid value. ; Read Debug Self Address Offset Register Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Debug 12 11...
Page 283: Table 11-10 Debug Status And Control Register Functions
0 = no instruction has completed execution since the last time this bit was cleared 1 = an instruction has completed execution since the last time this bit was cleared. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access...
Page 284: Table
If the external interface input DBGEN is LOW, this bit reads as 0. The programmed value is masked until DBGEN is HIGH, and at that time the read value reverts to the programmed value. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Debug...
Page 285: Table
ITR. This bit is set to 1 when a precise Data Abort occurs while the processor is in debug state and is cleared by writing to the DRCR[2]. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access...
Page 286: Table
0 = the processor is in normal state. This is the reset value. 1 = the processor is in debug state. The debugger can poll this bit to determine when the processor has entered debug state. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Debug...
Page 287 Debug communications channel on page 11-55. The Data Transfer Register, bits [31:0] contain the data to be transferred. ARM DDI 0363E ID013010 instructions, access the DTRTX instructions, access the DTRRX. Note Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Debug 11-18...
Page 288: Table 11-11 Data Transfer Register Functions
Function [31:1] Address This is the address of the watchpointed instruction. When a watchpoint occurs in ARM state, the WFAR contains the address of the instruction causing it plus an offset of occurs in Thumb state, the offset is plus Reserved RAZ.
Page 289: Table 11-13 Vector Catch Register Functions
0x00000008 0xFFFF0008 0x00000004 0xFFFF0004 0x00000000 0xFFFF0000 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access 8 7 6 5 4 3 2 1 0 Prefetch abort Figure 11-7 Vector Catch Register format Table 11-13 Vector Catch Register functions Function Do not modify on writes.
Page 290: Table 11-14 Debug State Cache Control Register Functions
The ITR is a write-only register. Reads from the ITR return an Unpredictable value. The Instruction Transfer Register, bits [31:0] contain the ARM instruction for the processor to execute while in debug state. The reset value of this register is Unpredictable.
Page 291: Table 11-15 Debug Run Control Register Functions
DSCR[0] until it reads 1. This bit always reads as zero. Writes are ignored when the processor is already in debug state. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Cancel memory request...
Page 292: Table 11-16 Breakpoint Value Registers Functions
20 19 16 15 14 13 Breakpoint Linked BRP address mask Reserved Figure 11-10 Breakpoint Control Registers format Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Bits Reset value Description [31:0] Breakpoint value 5 4 3 2 1 0...
Page 293: Table 11-17 Breakpoint Control Registers Functions
BRP is linked to another BRP that is not configured for linked context ID matching, it is Unpredictable whether a breakpoint debug event is generated. RAZ or SBZP. Do not modify on writes. On reads, the value returns zero. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Debug 11-24...
Page 294: Table 11-18 Meaning Of Bvr Bits [22:20]
= User b11 = any. Breakpoint enable: 0 = Breakpoint disabled. This is the reset value. 1 = Breakpoint enabled. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access ) +0 is accessed 0xFFFFFFFC ) +1 is accessed...
Page 295: Table 11-19 Watchpoint Value Registers Functions
Table 11-18 Meaning of BVR bits [22:20] (continued) Table 11-19 Watchpoint Value Registers functions Bits Description [31:2] Watchpoint address. [1:0] Reserved. Do not modify on writes. On reads, the value returns zero. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Debug 11-26...
Page 296: Table 11-20 Watchpoint Control Registers Functions
Should Be Zero. Otherwise the behavior is Unpredictable. • To watch for a write to any byte in an 8-byte aligned object of size 8 bytes, ARM recommends that a debugger sets WCR[28:24] to b00111, and WCR[12:5] to b11111111.
Page 297: Table
For all cases, the match refers to the privilege of the access, not the mode of the processor. Watchpoint enable: 0 = Watchpoint disabled. This is the reset value. 1 = Watchpoint enabled. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Debug ) +0 is...
Page 298: Table 11-21 Os Lock Status Register Functions
Secure invasive debug features implemented Secure invasive debug DBGEN features enabled Non-secure debug features Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Lock implemented bit Figure 11-12 OS Lock Status Register format Function Implemented Non-invasive debug enable field...
Page 299: Table 11-23 Prcr Functions
ARM DDI 0363E ID013010 a. Cortex-R4 does not implement the Security Extensions, so all the debug features are considered secure. Reserved Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Debug Hold internal reset Force internal reset No Power-down...
Page 300: Table 11-24 Prsr Functions
1 = the processor is currently held in reset. This bit reads 1 when nSYSPORESET is asserted. Reserved. Always zero. Reserved. Always one. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Debug Sticky reset status Reset status...
Page 301: Management Registers
Identification Registers. See Debug Identification Registers on page 11-35. Offset (hex) Register number 0xD00 0xD04 0xD08 0xD0C Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Table 11-25 Management Registers Table 11-26 Processor Identifier Registers Mnemonic Function MIDR Main ID Register...
Page 302: Table 11-27 Claim Tag Set Register Functions
0xD4C 0xD50 0xD54 Reserved Bits Field [31:8] Reserved [7:0] Claim tag set Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Mnemonic Function MPUIR MPU Type Register MPIDR Multiprocessor Affinity Register Alias of MIDR ID_PFR0 Processor Feature Register 0...
Page 303: Table 11-28 Functional Bits Of The Claim Tag Clear Register
[7:0] key to this register. To lock the debug registers, write any 0xC5ACCE55 Reserved Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access , indicating eight claim tags are implemented. Claim tag clear Figure 11-17 Claim Tag Clear Register format...
Page 304: Table 11-29 Lock Status Register Functions
, indicates that the sub-type of the device is processor core. [3:0] Main class , indicates that the main class of the device is debug logic. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Table 11-29 Lock Status Register functions Sub type...
Page 305: Size Description
4KB block, therefore this field is always Identifies the designer of the processor. This field consists of a 4-bit continuation code and a 7-bit identity code. Because the processor is designed by ARM, the continuation code is and the identity code is .
Page 306: Table 11-34 Peripheral Id Register 1 Functions
Indicates the number of blocks the debug component occupies. This field is always set to 0. Indicates the JEDEC JEP106 continuation code. For the processor, this value is 4. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access...
Page 307: Table 11-38 Component Identification Registers
Offset (hex) Register number 1020 0xFF0 1021 0xFF4 1022 0xFF8 1023 0xFFC Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Value Description Component Identification Register 0 0x0D Component Identification Register 1 0x90 Component Identification Register 2 0x05...
Page 308: Debug Events
The instruction is committed for execution. These debug events are generated whether the instruction passes or fails its condition code. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access instruction is committed for execution.
Page 309: Table 11-39 Processor Behavior On Debug Events
Ignore or Prefetch Abort (for None Ignore or Prefetch Abort (for Halting Debug state entry Monitor Debug exception Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Debug Action on halting debug event Ignore BKPT Debug state entry...
Page 310: Debug Exception
R14_abt as a regular Data Abort exception, that is, this register gets the address of the cancelled instruction plus setting the PC to the appropriate Data Abort vector. Note Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access 0x04 0x08...
Page 311: Table 11-40 Values In Link Register After Exceptions
Address of the instruction where the execution can resume address of the access that hit the watchpoint is in the WFAR. + 8 for ARM state + 4 for Thumb state. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access ) meaning instruction address...
Page 312: Table
Failure to follow these guidelines can lead to debug events occurring before the handler is able to save the context of the abort. This causes the corresponding registers to be overwritten, and results in Unpredictable software behavior. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Debug 11-43...
Page 313: Debug State
RA+4 Address of the instruction where the execution resumes. This is several instructions after the one that hit the watchpoint. RA+8 RA+4 instruction address. BKPT Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Debug ) meaning 11-44...
Page 314: Table
• The PC is frozen on entry to debug state. That is, it does not increment on the execution of ARM instructions. However, the processor still updates the PC as a response to instructions that explicitly modify the PC. •...
Page 315 The following restrictions apply to instructions executed through the ITR while in debug state: • with the exception of branch instructions and instructions that modify the CPSR, the processor executes any ARM instruction in the same manner as if it was not in debug state • the branch instructions •...
Page 316: Coprocessor Instructions
When an Undefined exception occurs in debug state, the behavior of the processor is as follows: • PC, CPSR, SPSR_und, and R14_und are unchanged • the processor remains in debug state • DSCR[8], sticky Undefined bit, is set. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Debug 11-47...
Page 317 DFSR remains unchanged • the processor does not act on this imprecise Data Abort on exit from the debug state, that is, the imprecise abort is discarded. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Debug 11-48...
Page 319: Cache Debug
(PMU). The processor can count cache accesses and misses over a period of time. See Chapter 6 Events and Performance Monitor. ARM DDI 0363E ID013010 Note , or to restore the original instruction BKPT Note Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Debug 11-50...
Page 320: 11.10 External Debug Interface
DBGROMADDR must be tied off to zero and DBGROMADDRV must be tied LOW. The value of these signals can be read from the Debug ROM Address Register (DRAR). ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Debug 11-51...
Page 321: Table 11-42 Authentication Signal Restrictions
When DBGEN is LOW, the processor behaves as if DSCR[15:14] equals b00 with the exception that halting debug events are ignored when this signal is LOW. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Non-invasive debug permitted...
Page 322 The values of the DBGEN and NIDEN signals can be determined by polling DSCR[17:16], DSCR[15:14], or the Authentication Status Register. ARM DDI 0363E ID013010 instruction that writes certain value to a control Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access ) instruction. Debug 11-53...
Page 323: 11.11 Using The Debug Functionality
This section provides some examples of using the processor debug functionality, both from the point of view of a software engineer writing code to run on an ARM processor and of a developer creating debug tools for the processor. In the former case, examples are given in ARM assembly language.
Page 324 • The mechanism for forcing the processor to execute ARM instructions, when the processor is in debug state. For more information, see Executing instructions in debug state on page 11-46.
Page 325 := ReadDebugRegister(34); until (dscr & (1<<29)); // Step 2. Read the value from DTRTX. dtr_val := ReadDebugRegister(35); return dtr_val; Example 11-5 Host to target data transfer (host end) Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Debug 11-56...
Page 326 Programming simple breakpoints and the byte address select When programming a simple breakpoint, you must set the byte address select bits in the control register appropriately. For a breakpoint in ARM state, this is simple. For Thumb state, you must calculate the value based on the address.
Page 327: Table 11-43 Values To Write To Bcr For A Simple Breakpoint
[8:5] [4:3] [2:1] byte_address_select := (1 << (address & 3)); byte_address_select := (3 << (address & 2)); byte_address_select := 15; Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Value to write Description Reserved 0b000 Breakpoint address mask...
Page 328: Table 11-44 Values To Write To Wcr For A Simple Watchpoint
:= (1 << (address & 7)); byte_address_select := (3 << (address & 6)); byte_address_select := (15 << (address & 4)); byte_address_select := 255; Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Value to write Description Reserved...
Page 329: Single-Stepping
0x0000A000 0b01111000 0x0000A000 0b11100000 0x0000B000 0b11111111 0x0000B000 0b11111110 Example 11-9 Setting a simple unaligned watchpoint Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Debug Second address Second byte value address mask Not required Not required Not required...
Page 330 SetComplexBreakpoint() instruction loads a link register that is saved at the start of the function, and instruction shown, it points back at the Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Debug indicates the value to set .
Page 331 // set the T bit to Thumb state state->pc := state->pc - 4; elseif (state->cpsr & (1<<24)) // Set the J bit to Jazelle state. Note: ARM Cortex-R4 does not support // Jazelle state but ARMv7 debug does. state->pc := state->pc - IMPLEMENTATION DEFINED value;...
Page 332 To read a single register, the debugger can use the sequence that Example 11-13 shows. This sequence depends on two other sequences, Executing an ARM instruction through the ITR on page 11-54 and Target to host data transfer (host end) on page 11-56.
Page 333 Example 11-17 on page 11-65 shows the code for writing the CPSR. ARM DDI 0363E ID013010 Note Note Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Debug Example 11-15 Reading the PC Example 11-16 Reading the CPSR...
Page 334: Reading Memory
Example 11-19 Checking for an abort after memory access // Step 2. Clear the sticky flag by writing DRCR[2]. WriteDebugRegister(36, 1<<2); return true; Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Example 11-17 Writing the CPSR Example 11-18 Reading a byte of memory...
Page 335 // Step 4. Read the value of R1 that contains the data at the // address. *data++ := ReadRegister(1); --nbytes; Note Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Example 11-21 Reading a word of memory Debug 11-66...
Page 336 // Write stalls until the DTRRX is ready. ARM DDI 0363E ID013010 Example 11-22 Changing the DTR access mode Example 11-23 Reading registers in stall mode Example 11-24 Writing registers in stall mode Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Debug 11-67...
Page 337 // Step 11. Restore the corrupted register r0. WriteRegister(0, saved_r0); ARM DDI 0363E ID013010 Note Example 11-25 Reading a block of words of memory *data++ = ReadDebugRegister(35); --nwords; Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Debug 11-68...
Page 338 Accessing coprocessor registers The sequence for accessing coprocessor registers is the same for the PC and CPSR. That is, you must first execute an instruction to transfer the register to an ARM register, then read the value back through the DTR.
Page 339 // Step 3. Read the value of R0 that now contains the CP register. CP15c1 := ReadRegister(0); // Step 4. Restore the value of R0. WriteRegister(0, saved_r0); return CP15c1; ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Debug + (opc2<<5)); 11-70...
Page 340: 11.12 Debugging Systems With Energy Management Capabilities
Recovery involves a reset of the processor after the power level has been restored, and reinstallation of the processor state. leaves standby retires the Wait-For-Interrupt ( ) instruction enters debug state. instruction from the pipeline. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Debug 11-71...
Page 341 DBGNOPWRDWN signal to 1 might not cause the processor to power up. The effect of setting DBGNOPWRDWN to 1 when the processor is already powered down is implementation-defined, and is up to the system designer. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Debug 11-72...
Page 342: Chapter 12 Fpu Programmer's Model
General-purpose registers on page 12-3 • System registers on page 12-4 • Modes of operation on page 12-10 • Compliance with the IEEE 754 standard on page 12-11. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access 12-1...
Page 343: About The Fpu Programmer's Model
Manual for information on the VFPv3 instruction set. 12.1.1 FPU functionality The FPU is an implementation of the ARM Vector Floating Point v3 architecture, with 16 double-precision registers (VFPv3-D16). It provides floating-point computation functionality that is compliant with the ANSI/IEEE Std 754-1985, IEEE Standard for Binary Floating-Point Arithmetic, referred to as the IEEE 754 standard.
Page 344: General-Purpose Registers
12.2 General-purpose registers The FPU implements a VFP register bank. This bank is distinct from the ARM register bank. You can reference the VFP register bank using two explicitly aliased views. Figure 12-1 shows the two views of the register bank and the way the word and doubleword registers overlap.
Page 345: System Registers
Register FPEXC EN=0 FPSID Permitted FPSCR Not permitted MVFR0, MVFR1 Permitted FPEXC Permitted Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access FPU Programmer’s Model Table 12-1 VFP system registers Access type Read-only Read/write Read/write Read-only Read-only Table 12-2 Accessing VFP system registers...
Page 346: Table 12-3 Fpsid Register Bit Functions
Part number [7:4] Variant [3:0] Revision a. For details of the Common VFP subarchitecture see the ARM Architecture Reference Manual. ARM DDI 0363E ID013010 Note This is a change in VFPv3 compared to VFPv2. User code must issue a system call to determine the features that are supported.
Page 347: Floating-Point Status And Control Register, Fpscr
= round towards minus infinity (RM) mode b11 = round towards zero (RZ) mode. Indicates the vector stride, reset value is Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access FPU Programmer’s Model 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
Page 348: Table
Overflow cumulative flag, resets to zero Division by Zero cumulative flag, resets to zero Invalid Operation cumulative flag, resets to zero Reserved Figure 12-4 Floating-Point Exception Register format Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access FPU Programmer’s Model Reserved 12-7...
Page 349: Table 12-5 Floating-Point Exception Register Bit Functions
Double precision supported in VFPv3: [7:4] Single precision supported in VFPv3: [3:0] 16x64-bit media register bank supported: Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access FPU Programmer’s Model 12 11 Figure 12-5 MVFR0 Register format Table 12-6 MVFR0 Register bit functions...
Page 350: Table 12-7 Mvfr1 Register Bit Functions
0b0000 [7:4] Propagation of NaN values supported for VFP: [3:0] Full denormal arithmetic supported for VFP: Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access FPU Programmer’s Model 12 11 Figure 12-6 MVFR1 Register format Table 12-7 MVFR1 Register bit functions...
Page 351: Modes Of Operation
ARM DDI 0363E ID013010 operations as zeros in the operation. Exceptions that operations and are not affected by flush-to-zero mode. A result that is tiny, as Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access FPU Programmer’s Model , and...
Page 352: Compliance With The Ieee 754 Standard
Signaling NaN (SNaN). A one indicates a Quiet NaN (QNaN). Two NaN values are treated as different NaNs if they differ in any bit. Table 12-8 shows the default NaN values in both single-precision and double-precision. Processing of input NaNs for ARM floating-point functionality and libraries is defined as follows: •...
Page 353: Table 12-9 Qnan And Snan Handling
IEEE 754 standard to generate Underflow exceptions. In flush-to-zero mode, results that are tiny before rounding, as described in the IEEE 754 standard, are flushed to a zero, and the UFC flag, FPSCR[3], is set. See the ARM Architecture Reference Manual for information on flush-to-zero mode.
Page 354 You can mask each of these outputs masked by setting the corresponding bit in the Secondary Auxiliary Control Register. See Auxiliary Control Registers on page 4-38 for more information. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access FPU Programmer’s Model 12-13...
Page 355 Programming and reading Integration Test Registers on page 13-3 • Summary of the processor registers used for integration testing on page 13-4 • Processor integration testing on page 13-5. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access 13-1...
Page 356: About Integration Test Registers
For more information about the Integration Test Registers and the Integration Mode Control Register see the ARM Architecture Reference Manual. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Integration Test Registers 13-2...
Page 357: Programming And Reading Integration Test Registers
• every transfer takes at least two cycles. For more information on APB transfers see AMBA 3 APB Protocol v1.0 Specification. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Integration Test Registers 13-3...
Page 358: Summary Of The Processor Registers Used For Integration Testing
See ITMISCOUT Register (Miscellaneous Outputs) on page 13-8 See ITMISCIN Register (Miscellaneous Inputs) on page 13-8 See Integration Mode Control Register (ITCTRL) on page 13-9 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Integration Test Registers 13-4...
Page 359: Processor Integration Testing
This section describes the behavior and use of the Integration Test Registers that are in the processor. It also describes the Integration Mode Control Register that controls the use of the Integration Test Registers. For more information about the ITCTRL see the ARM Architecture Reference Manual.
Page 360: Table 13-3 Input Signals That Can Be Read By The Integration Test Registers
• ARM strongly recommends that the processor is halted while in debug state, because toggling input and output pins might have an unwanted effect on the operation of the processor. You must not set the ITCTRL Register until the processor has halted.
Page 361: Table 13-4 Itetmif Register Bit Assignments
ETMDA[31] ETMDA[0] ETMDCTL[11] ETMDCTL[0] ETMIA[31] ETMIA[1] ETMICTL[13] ETMICTL[0] a. Not available on r0px revisions of the processor. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Integration Test Registers 5 4 3 ETMICTL[0] ETMICTL[13] ETMIA[1] ETMIA[31] ETMDCTL[0] ETMDCTL[11]...
Page 362: Table 13-5 Itmiscout Register Bit Assignments
DBGTRIGGER [7:6] ETMWFIPENDING nPMUIRQ COMMTX COMMRX DBGACK is read-only. Figure 13-3 on page 13-9 shows the OxEFC Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Integration Test Registers 5 4 3 DBGRESTARTED DBGTRIGGER Reserved ETMWFIPENDING nPMUIRQ Reserved...
Page 363: Table 13-6 Itmiscin Register Bit Assignments
Read value of nIRQ input pin. Read value of EDBGRQ input pin. at offset 0x3C0 0xF00 Reserved Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Integration Test Registers 10 9 8 7 4 3 2 Reserved Reserved...
Page 364: Table 13-7 Itctrl Register Bit Assignments
Writing to the ITCTRL register controls whether the processor is in its default functional mode, or in integration mode, where the inputs and outputs of the device can be directly controlled for the purpose of integration testing or topology detection. For more information see the ARM Architecture Reference Manual.
Page 365 • Floating-point register transfer instructions on page 14-29 • Floating-point load/store instructions on page 14-30 • Floating-point single-precision data processing instructions on page 14-32 ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access 14-1...
Page 366 • Floating-point double-precision data processing instructions on page 14-33 • Dual issue on page 14-34. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Cycle Timings and Interlock Behavior 14-2...
Page 367: About Cycle Timings And Interlock Behavior
ARM DDI 0363E ID013010 ;Result latency one ;Register R1 required by ALU ;Result latency two ;Register R1 required by ALU ;Result latency two Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Cycle Timings and Interlock Behavior 14-3...
Page 368: Conditional Instructions
;no penalty because R1 is a Late register ;Result latency one plus two cycles ;plus two because register R3 is Very Early Note Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Cycle Timings and Interlock Behavior Table 14-1 Definition of cycle timing terms...
Page 369 There is a data dependency between two instructions in the pipeline, resulting in the Iss stage being stalled until the processor resolves the dependency. 14.1.5 Assembler language syntax The syntax used throughout this chapter is unified assembler and the timings apply to ARM and Thumb instructions. ARM DDI 0363E ID013010...
Page 370: Register Interlock Examples
LDR to generate R1. ARM DDI 0363E ID013010 instructions have a result latency of one. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Cycle Timings and Interlock Behavior instructions. Table 14-2 Register interlock examples...
Page 371: Data Processing Instructions
<Rm> with any data processing instruction except for a Early Late Cycles <Rm> > <Rm> <Rs> Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Cycle Timings and Interlock Behavior ADDW , and SUBW Result Comments latency Normal cases.
Page 372: Example Interlocks
The register containing the shift distance is an Early Reg. For example, the following sequence takes three cycles to execute: ADD R1, R2, R3 ADD R4, R2, R4, LSL R1 ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Cycle Timings and Interlock Behavior 14-8...
Page 373: Qadd, Qdadd, Qsub, And Qdsub Instructions
Table 14-5 QADD, QDADD, QSUB, and QDSUB instruction cycle timing behavior Instructions QADD QSUB QDADD QDSUB Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Cycle Timings and Interlock Behavior , and instructions. QADD QDADD...
Page 374: Media Data-Processing
SHASX SHSAX UQASX UQSAX UHASX UHSAX SBFX UBFX a. A shift of zero makes <Rm> Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Cycle Timings and Interlock Behavior Cycles Early Reg Result latency <Rn> <Rm> <Rm> <Rm>...
Page 375: Sum Of Absolute Differences (Sad)
USAD8 instruction. Takes two cycles. The Result Latency is one less because the result is used as the accumulate for a subsequent USADA8 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Cycle Timings and Interlock Behavior Cycles...
Page 376: Multiplies
SMMUL SMMULR <Rn>, <Rm> SMMLA SMMLAR <Rn>, <Rm> SMMLS SMMLSR <Rn>, <Rm> Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Cycle Timings and Interlock Behavior Late Reg Result latency <Ra> 3, 3 3, 3 3, 3 <RdLo>, <RdHi>...
Page 377 Table 14-9 Example multiply instruction cycle timing behavior (continued) Example Cycles instruction SMLALD SMLALDX SMLSLD SMLSLDX UMAAL Note Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Cycle Timings and Interlock Behavior Early Reg Late Reg Result latency 2, 2 <Rn>, <Rm> 2, 2 <Rn>, <Rm>...
Page 378: Divide
UDIV clz(B) - clz(A) + 1 instruction A divided by B is given by: SDIV clz(B) - clz(A) + 1 Note Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Cycle Timings and Interlock Behavior instructions. UDIV SDIV...
Page 379: Branches
Condition code passes Correct condition prediction Incorrectly predicted Condition code fails Condition code passes Condition code fails Condition code passes Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Cycle Timings and Interlock Behavior , and CBNZ 14-15...
Page 380: 14.10 Processor State Updating Instructions
Table 14-11 Processor state updating instructions cycle timing behavior Instruction MSR SPSR CPS <effect> <iflags> CPS <effect> <iflags>, #<mode> SETEND Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Cycle Timings and Interlock Behavior , and instructions. SETEND...
Page 381: 14.11 Single Load And Store Instructions
(LDR) <addr_md_1cycle> Table 14-13 Cycle timing behavior for loads to the PC Memory Result Cycles cycles latency Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Cycle Timings and Interlock Behavior LDRHT LDRSBT LDRSHT LDRT LDRB instructions.
Page 382: Table 14-14 And Ldr Example Instruction Explanation
<Rn>, <Rm> <Rn>, <Rm> <Rn>,<Rm> <Rn>,<Rm> aligned the following instruction sequence take three cycles to execute: Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Cycle Timings and Interlock Behavior Comments Conditional predicted incorrectly, but return stack predicted correctly .
Page 383 LDR R6, [R2, #0X10]! LDR R7, [R2, #0X20]! ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Cycle Timings and Interlock Behavior 14-19...
Page 384: 14.12 Load And Store Double Instructions
Cycles base writeback <addr_md_1cycle> <addr_md_3cycle> <addr_md_1cycle> Very Early Reg <Rn> <Rn>, <Rm> <Rn> <Rn>, <Rm> <Rn>,<Rm> Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Cycle Timings and Interlock Behavior instructions. LDRD STRD instructions. LDRD STRD Result Memory...
Page 385: 14.13 Load And Store Multiple Instructions
ID013010 , is a Very Early Reg. <Rn> Cycles with base Cycles register write-back Note Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Cycle Timings and Interlock Behavior , and instructions. PUSH Memory Result latency Result latency...
Page 386: Table 14-18 Cycle Timing Behavior Of Load Multiples, With Pc In The Register List (64-Bit Aligned)
R7 has instruction takes five cycles to execute: instruction takes seven cycles to execute, because instruction takes five cycles to execute: PUSH Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Cycle Timings and Interlock Behavior to the Comments...
Page 387 In the examples, R0 and use the ARM DDI 0363E ID013010 Note are 64-bit aligned addresses. The instructions register for the base address. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Cycle Timings and Interlock Behavior always PUSH 14-23...
Page 388: 14.14 Rfe And Srs Instructions
Table 14-19 RFE and SRS instructions cycle timing behavior Example instruction Address doubleword aligned RFEIA <Rn> SRSIA #<mode> Address not doubleword aligned RFEIA <Rn> SRSIA #<mode> Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Cycle Timings and Interlock Behavior instructions. instructions. Cycles Memory cycles 14-24...
Page 389: 14.15 Synchronization Instructions
STREXD <Rd>, <Rt>, <Rt2>, [Rn] SWP <Rt>, <Rt2>, [Rn] SWPB <Rt>, <Rt2>, [Rn] a. Address must be 64-bit aligned. , and Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Cycle Timings and Interlock Behavior CLREX LDREX , and...
Page 390: 14.16 Coprocessor Instructions
Table 14-21 Coprocessor instructions cycle timing behavior Instruction Cycles MCR <cond> MRC <cond> Note Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Cycle Timings and Interlock Behavior instructions to CP14, the Result latency Comments Condition code passes...
Page 391: 14.17 Svc, Bkpt, Undefined, And Prefetch Aborted Instructions
Undefined, prefetch aborted instructions cycle timing behavior. Table 14-22 SVC, BKPT, Undefined, prefetch aborted instructions cycle timing behavior ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Cycle Timings and Interlock Behavior , Undefined instruction,...
Page 392: 14.18 Miscellaneous Instructions
YIELD instruction stalls the pipeline for a variable number of cycles, depending on the current Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Cycle Timings and Interlock Behavior Late Reg...
Page 393: 14.19 Floating-Point Register Transfer Instructions
VMOV <Rt>, <Rt2>, <Sm>, <Sm1> VMOV <Dm>, <Rt>, <Rt2> VMOV <Rt>, <Rt2>, <Dm> VMSR <spec_reg>, <Rt> VMRS <Rt>, <spec_reg> VMRS APSR_nzcv, FPSCR Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Cycle Timings and Interlock Behavior has completed FMXR VMLA.F32 VMLS.F32...
Page 394: 14.20 Floating-Point Load/Store Instructions
ARM DDI 0363E ID013010 Note Table 14-25 Floating-point load/store instructions cycle timing behavior Cycles/ Cycles with memory writeback (!) cycles Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Cycle Timings and Interlock Behavior Result Result latency latency (base Comments...
Page 395 VLDM{mode}.64 <Rn>{!}, {d1-d3} VLDM{mode}.64 <Rn>{!}, {d1-d4} ARM DDI 0363E ID013010 Cycles/ Cycles with memory writeback (!) cycles Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Cycle Timings and Interlock Behavior Result Result latency latency (base Comments (load) register, <Rn>)
Page 396: Floating-Point Single-Precision Data Processing Instructions Cycle Timing Behavior
VCVT.F32.U16 VCVT.F32.S32 i. Also VCVT.U32.F32 VCVTR.S32.F32 j. Also VCVT.U16.F32 VCVT.S32.F32 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Cycle Timings and Interlock Behavior , data and immediate moving instructions VMUL.F32 , and , and comparison VNEG.F32 “VMOV <Sd>, <Sm>”...
Page 397: Floating-Point Double-Precision Data Processing Instructions Cycle Timing Behavior
VCVT.F64.S32 g. Also VCVT.U32.F64 VCVTR.S32.F64 h. Also , and VCVT.U16.F64 VCVT.S32.F64 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Cycle Timings and Interlock Behavior , data and immediate moving instructions VMUL.F64 , and , and comparison VNEG.F64 “VMOV <Dd>, <Dm>”...
Page 398: 14.23 Dual Issue
The first instruction must not use the PC as a destination register. • Both instructions must belong to the same instruction set, ARM or Thumb. • There must be no data dependency between the two instructions. That is, the second instruction must not have any source registers that are destination registers of the first instruction.
Page 399: Table 14-28 Permitted Instruction Combinations
VMSR , excluding "VMOV.S32 <Sd>, , and VABS.F32 VNEG.F32 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Cycle Timings and Interlock Behavior Second instruction B #immed Any data processing instruction that does not require a shift by a register value.
Page 400: First Instruction
VCVTR.U32.F32 VCVT.U32.F32 VCVTR.S32.F32 , and "VMOV <Rt>, <Dn[x]>" SMMUL SMMLA SMMLS Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Cycle Timings and Interlock Behavior Second instruction As for Case B1. Any single-precision CDP , excluding multiply-accumulate instructions...
Page 401: Chapter 15 Ac Characteristics
This chapter gives the timing parameters for the processor. It contains the following sections: • Processor timing on page 15-2 • Processor timing parameters on page 15-3. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access 15-1...
Page 402: Processor Timing
Specification. For the relevant timing of the APB write and read transfers, and the error response, see the AMBA 3 APB Protocol v1.0 Specification. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access AC Characteristics 15-2...
Page 403: Processor Timing Parameters
Clock uncertainty Clock uncertainty Clock uncertainty Clock uncertainty Clock uncertainty Clock uncertainty Clock uncertainty Clock uncertainty Clock uncertainty Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access AC Characteristics Input delay Signal name maximum nRESET nSYSPORESET PRESETDBGn nCPUHALT...
Page 404: Table 15-3 Interrupt Input Ports Timing Parameters
Clock uncertainty Clock uncertainty Clock uncertainty Clock uncertainty Clock uncertainty Clock uncertainty Clock uncertainty Clock uncertainty Clock uncertainty Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access AC Characteristics Input delay Signal name maximum PARLVRAM ENTCM1IF SLBTCMSB RMWENRAM[1:0]...
Page 405: Table 15-5 Axi Slave Input Port Timing Parameters
Clock uncertainty Clock uncertainty Clock uncertainty Clock uncertainty Clock uncertainty Clock uncertainty Clock uncertainty Clock uncertainty Clock uncertainty Clock uncertainty Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access AC Characteristics Input delay Signal name maximum RVALIDM BPARITYM RPARITYM...
Page 406: Table 15-6 Debug Input Ports Timing Parameters
Clock uncertainty Clock uncertainty Table 15-7 ETM input ports timing parameters Input delay minimum Clock uncertainty Clock uncertainty Clock uncertainty Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access AC Characteristics Input delay Signal name maximum AWPARITYS WPARITYS...
Page 407: Table 15-8 Test Input Ports Timing Parameters
Clock uncertainty Clock uncertainty Clock uncertainty Clock uncertainty Clock uncertainty Clock uncertainty Clock uncertainty Clock uncertainty Clock uncertainty Clock uncertainty Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access AC Characteristics Input delay Signal name maximum RSTBYPASS MBTESTON MBISTDIN[71:0]...
Page 408: Table 15-10 Miscellaneous Output Port Timing Parameter
Table 15-12 AXI master output port timing parameters Output delay minimum Clock uncertainty Clock uncertainty Clock uncertainty Clock uncertainty Clock uncertainty Clock uncertainty Clock uncertainty Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access AC Characteristics Input delay Signal name maximum B1TCWAIT B1TCLATEERROR B1TCRETRY...
Page 409: Table 15-13 Axi Slave Output Ports Timing Parameters
Clock uncertainty Clock uncertainty Table 15-13 AXI slave output ports timing parameters Output delay minimum Clock uncertainty Clock uncertainty Clock uncertainty Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access AC Characteristics Output delay Signal name maximum AWPROTM[2:0] AWUSERM[4:0]...
Page 410: Table 15-14 Debug Interface Output Ports Timing Parameters
Clock uncertainty Clock uncertainty Clock uncertainty Clock uncertainty Clock uncertainty Clock uncertainty Clock uncertainty Clock uncertainty Clock uncertainty Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access AC Characteristics Output delay Signal name maximum BRESPS[1:0] BVALIDS ARREADYS RIDS[7:0]...
Page 411: Table 15-15 Etm Interface Output Ports Timing Parameters
Clock uncertainty Clock uncertainty Clock uncertainty Clock uncertainty Clock uncertainty Clock uncertainty Clock uncertainty Clock uncertainty Clock uncertainty Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access AC Characteristics Output delay Signal name maximum ETMICTL[13:0] ETMIA[31:1] ETMDCTL[11:0] ETMDA[31:0]...
Page 412: Table 15-18 Fpu Output Port Timing Parameters
Table 15-18 FPU output port timing parameters Output delay minimum Clock uncertainty Clock uncertainty Clock uncertainty Clock uncertainty Clock uncertainty Clock uncertainty Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access AC Characteristics Output delay Signal name maximum ATCADDRPTY B0TCEN0 B0TCEN1...
Page 413 The timing parameters for the dual-redundant core compare logic output buses, DCCMOUT[7:0] and DCCMOUT2[7:0], are implementation-defined. Contact the implementer of the macrocell you are working with. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access AC Characteristics 15-13...
Page 414: Appendix A Processor Signal Descriptions
ETM interface signals on page A-19 • Test signals on page A-20 • MBIST signals on page A-21 • Validation signals on page A-22 • FPU signals on page A-23. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access...
Page 415: Table
Means the input is synchronised inside the processor, so the input can be driven from any clock. Means the input must be tied to a fixed value. Means the input must only be changed under reset. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Processor Signal Descriptions...
Page 416: A.2 Global Signals
Indicates that the processor is in Standby mode and the processor clock is stopped. You can use this signal for TCMs RAM clock gating. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Processor Signal Descriptions Table A-1 Global signals...
Page 417: A.3 Configuration Signals
= 64KB b1000 = 128KB b1001 = 256KB b1010 = 512KB b1011 = 1MB b1100 = 2MB b1101 = 4MB b1110 = 8MB. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Processor Signal Descriptions Table A-2 Configuration signals...
Page 418 Selects between odd and even parity for caches, TCMs, and Reset buses. See Chapter 8 Level One Memory System: Tie LOW for even parity Tie HIGH for odd parity. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Processor Signal Descriptions Table A-2 Configuration signals (continued)
Page 419: Table
Use most significant bit of BTCM address to select B1TCM if this signal is HIGH. Use bit [3] of the BTCM address if this signal is LOW. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Processor Signal Descriptions...
Page 420: Interrupt Signals, Including Vic Interface Signals
Address of the IRQ. This signal must be stable when IRQADDRV is asserted. Output CLKIN Acknowledges interrupt. Output CLKIN Interrupt request by Performance Monitor Unit (PMU). Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Processor Signal Descriptions Table A-3 Interrupt signals...
Page 421: A.5 L2 Interface Signals
Indicates the size of the transfer. Output CLKIN Provides decode information for the write address channel. See Table 9-3 on page 9-5 for information about the encoding of this signal. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Processor Signal Descriptions Note...
Page 422 Input CLKIN Address ready. The slave uses this signal to indicate that it can accept the address. Output CLKIN Indicates the size of the transfer. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Processor Signal Descriptions...
Page 423: Table A-5 Axi Master Port Error Detection Signals
(bit[0]) channels Table A-6 AXI slave port signals for the L2 interface Clocking Description CLKIN Clock enable for the AXI slave port. CLKIN Transfer start address. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Processor Signal Descriptions A-10...
Page 424 AXI specification. CLKIN Address ready. The slave uses this signal to indicate that it can accept the address. CLKIN Indicates the size of the transfer. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Processor Signal Descriptions A-11...
Page 425: Table A-7 Axi Slave Port Error Detection Signals
Parity bit for read data channel CLKIN Parity error indication for read address (bit [2]), write data (bit [1]), and write address (bit [0]) channels. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Processor Signal Descriptions A-12...
Page 426: Tcm Interface Signals
CLKIN Input CLKIN Input CLKIN Input CLKIN Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Processor Signal Descriptions Table A-8 ATCM port signals Description Data from ATCM Parity or ECC code from ATCM Error detected by ATCM...
Page 427: Table A-10 B1Tcm Port Signals
CLKIN Output CLKIN Output CLKIN Output CLKIN Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Processor Signal Descriptions Table A-9 B0TCM port signals (continued) Description Late error from B0TCM Access to B1TCM must be retried Parity formed from B0TCM address output...
Page 428 CLKIN Output CLKIN Output CLKIN Output CLKIN Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Processor Signal Descriptions Table A-10 B1TCM port signals (continued) Description Address for B1TCM data RAM Byte strobes for direct write B1TCM RAM access is sequential...
Page 429: Dual Core Interface Signals
Direction Clocking Input Output Input Output Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Processor Signal Descriptions Table A-11 Dual core interface signals Description Dual core compare logic input control bus Dual core compare logic output control bus...
Page 430: Debug Interface Signals
Output Output Output Output Output Input Output Output Input Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Processor Signal Descriptions Table A-12 Debug interface signals Table A-13 Debug miscellaneous signals Clocking Description Debug enable Non-invasive debug enable...
Page 431 Table A-13 Debug miscellaneous signals (continued) Direction Input Input Input a. Not available in r0px revisions of the processor. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Processor Signal Descriptions Clocking Description Tie-off Debug ROM physical address valid...
Page 432: Etm Interface Signals
Output CLKIN Input CLKIN Input CLKIN Input CLKIN Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Processor Signal Descriptions Table A-14 ETM interface signals Description ETM instruction control bus ETM instruction address ETM data control bus ETM data address...
Page 433: A.10 Test Signals
Test signals Table A-15 shows the test signals. ARM DDI 0363E ID013010 Signal RSTBYPASS a. Design for test only. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Processor Signal Descriptions Table A-15 Test signals Direction Clocking Description...
Page 434: A.11 Mbist Signals
ARM DDI 0363E ID013010 Signal MBTESTON MBISTDIN[77:0] MBISTADDR[19:0] MBISTCE MBISTSEL[4:0] MBISTWE [7:0] MBISTDOUT[77:0] Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Processor Signal Descriptions Table A-16 MBIST signals Direction Clocking Description Input CLKIN MBIST test is enabled...
Page 435: A.12 Validation Signals
ID013010 Signal Direction VALEDBGRQ Output nVALIRQ Output nVALFIQ Output nVALRESET Output Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Processor Signal Descriptions Table A-17 Validation signals Clocking Description CLKIN Debug request CLKIN Request for an interrupt CLKIN...
Page 436: Table A-18 Fpu Signals
Output CLKIN FPDZC Output CLKIN FPIDC Output CLKIN Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Processor Signal Descriptions Table A-18 FPU signals Description Masked floating-point inexact exception Masked floating-point overflow exception Masked floating-point underflow exception Masked floating-point invalid operation exception...
Page 437: Appendix Becc Schemes
This appendix describes some of the advantages and disadvantages of the different Error Checking and Correction (ECC) schemes for the TCMs. It contains the following section: • ECC scheme selection guidelines on page B-2. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access...
Page 438: Ecc Scheme Selection Guidelines
TCM a program performs many unaligned accesses to data in a TCM a program performs many byte, halfword, and word accesses to data in a TCM. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access ECC Schemes...
Page 439: Table C-1 Differences Between Issue B And Issue C
Added sections ARM DDI 0363E ID013010 Table C-1 Differences between issue B and issue C Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Location • About the programmer’s model on page 2-2 •...
Page 440 Clarified the description of the handling of TCM external faults Added dormant mode description ARM DDI 0363E ID013010 Table C-1 Differences between issue B and issue C (continued) Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Revisions Location Table 4-2 on page 4-9 Table 4-2 on page 4-9 •...
Page 441: Table C-2 Differences Between Issue C And Issue D
ARM DDI 0363E ID013010 Table C-1 Differences between issue B and issue C (continued) Table C-2 Differences between issue C and issue D Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Revisions Location Dormant mode on page 10-3...
Page 442: Glossary
Abort, and an internal or External Abort. See also Data Abort, External Abort and Prefetch Abort. An abort model is the defined behavior of an ARM processor in response to a Data Abort exception. Abort model Different abort models behave differently with regard to load and store instructions that specify base register write-back.
Page 443 Harvard architecture, instruction set architecture, ARMv6 architecture. A word that specifies an operation for an ARM processor to perform. ARM instructions must ARM instruction be word-aligned.
Page 444 Write address channel. Write data channel. Write response channel. Read address channel. Read data channel. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access slave AXI slave interface handshake has asserted, but for which...
Page 445 The maximum number of active write transactions that a slave interface can accept. The number of active write transactions for which the slave interface can receive data. This is counted from the earliest transaction. Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Glossary Glossary-4...
Page 446 16-beat bursts, and to specify how the addresses are incremented. See also Beat. An 8-bit data item. Byte ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Glossary Glossary-5...
Page 447 The ARM architecture supports byte-invariant systems in ARMv6 and later versions. When byte-invariant support is selected, unaligned halfword and word memory accesses are also supported.
Page 448 See Write-back. Copy back In the context of an ARM Integrator, a core module is an add-on development board that Core module contains an ARM processor and local memory. Core modules can run standalone, or can be stacked onto Integrator motherboards.
Page 449 A hardware macrocell that, when connected to a processor core, outputs instruction and data trace information on a trace port. The ETM provides processor driven trace through a trace port compliant to the ATB protocol. The JTAG-based hardware provided by debuggable ARM processors to aid debugging in EmbeddedICE-RT real-time.
Page 450 Most processors are built in compliance with the standard either in hardware or in a combination of hardware and software. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Glossary Glossary-9...
Page 451 See also Big-endian memory. Load/store architecture A processor architecture where data-processing operations only operate on register contents, not directly on memory contents. ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Glossary Glossary-10...
Page 452 These are combined as a single macrocell, that can be fabricated on an integrated circuit. Reads are defined as memory operations that have the semantics of a load. That is, the ARM Read instructions...
Page 453: Rounding Mode
Significand bit to the left of the implied binary point and a fraction field to the right. See Saved Program Status Register SPSR ARM DDI 0363E ID013010 Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Glossary Glossary-12...
Page 454 Unaligned size is said to be unaligned. For example, a word stored at an address that is not divisible by four. Indicates an instruction that generates an Undefined instruction trap. See the ARM Architecture Undefined Reference Manual for more information on ARM exceptions.
Page 455 See also Byte-invariant. Writes are defined as operations that have the semantics of a store. That is, the ARM instructions Write STRH...
Page 456 ID013010 Block address Index Word Cache way Line number Cache tag RAM (way number) Copyright © 2009 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access Byte Cache set Cache line Word number Cache data RAM Read data (way that corresponds)

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ARM Cortex r1p3 Technical Reference Manual

Preface

Chapter 1 Introduction

Chapter 2 Programmer's Model

Chapter 3 Processor Initialization, Resets, and Clocking

Chapter 4 System Control Coprocessor

Chapter 5 Prefetch Unit

Chapter 6 Events and Performance Monitor

Chapter 7 Memory Protection Unit

Chapter 8 Level One Memory System

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