ARM Cortex-A53 MPCore Technical Reference Manual

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ARM

Cortex

-A53 MPCore Processor

Revision: r0p2

Technical Reference Manual

ARM DDI 0500D (ID021414)

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Summary of Contents for ARM Cortex-A53 MPCore

Page 2 This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.
Page 3: Table Of Contents
Power management ....................2-16 Chapter 3 Programmers Model About the programmers model ................3-2 ARMv8-A architecture concepts ................3-4 Chapter 4 System Control About system control ....................4-2 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 4 11.10 External debug interface ..................11-37 11.11 ROM table ......................11-41 Chapter 12 Performance Monitor Unit 12.1 About the PMU ...................... 12-2 12.2 PMU functional description ..................12-3 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 5 IT Block ............B-4 Load/Store accesses crossing page boundaries ............. B-5 ARMv8 Debug unpredictable behaviors ..............B-6 Other unpredictable behaviors ................B-11 Appendix C Revisions ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 6: Preface
This preface introduces the ARM Cortex -A53 MPCore Processor Technical Reference ® ® Manual. It contains the following sections: • About this book on page vii. • Feedback on page ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 7: About This Book
Preface About this book This book is for the Cortex-A53 MPCore processor. This is a cluster device that has between one and four cores. Product revision status The rmpn identifier indicates the revision status of the product described in this book, for example, r1p2, where: Identifies the major revision of the product, for example, r1.
Page 8: Typographical Conventions
Read this for a description of the technical changes between released issues of this book. Glossary The ARM Glossary is a list of terms used in ARM documentation, together with definitions for ® those terms. The ARM Glossary does not contain terms that are industry standard unless the ®...
Page 9: Timing Diagrams
Encloses replaceable terms for assembler syntax where they appear in code or code fragments. For example: MRC p15, 0 <Rd>, <CRn>, <CRm>, <Opcode_2> Used in body text for a few terms that have specific technical meanings, that are defined in the ARM Glossary.
Page 10: Other Publications
This section lists relevant documents published by third parties: • ANSI/IEEE Std 754-2008, IEEE Standard for Binary Floating-Point Arithmetic. Note ARM floating-point terminology is largely based on the earlier ANSI/IEEE Std 754-1985 issue of the standard. See the ARM Architecture Reference Manual ARMv8, for ARMv8-A ®...
Page 11: Feedback
ARM also welcomes general suggestions for additions and improvements. Note ARM tests the PDF only in Adobe Acrobat and Acrobat Reader, and cannot guarantee the quality of the represented document when used with any other PDF reader. ARM DDI 0500D Copyright ©...
Page 12 1-6. • Implementation options on page 1-7. • Test features on page 1-9. • Product documentation and design flow on page 1-10. • Product revisions on page 1-12. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 13: Chapter 1 Introduction
The Cortex-A53 processor has one to four cores, each with an L1 memory system and a single shared L2 cache. Figure 1-1 shows an example of a Cortex-A53 MPCore configuration with four cores and either an ACE or a CHI interface. Cortex-A53 processor...
Page 14: Compliance
Support for both AArch32 and AArch64 Execution states. • Support for all exception levels, EL0, EL1, EL2, and EL3, in each execution state. • The A32 instruction set, previously called the ARM instruction set. • The T32 instruction set, previously called the Thumb instruction set. •...
Page 15 Introduction 1.2.3 Generic Interrupt Controller architecture The Cortex-A53 processor implements the Generic Interrupt Controller (GIC) v4 architecture. The Cortex-A53 processor includes only the GIC CPU Interface. See the ARM Generic ® Interrupt Controller Architecture Specification. 1.2.4 Generic Timer architecture The Cortex-A53 processor implements the ARM Generic Timer architecture. See the ARM ®...
Page 16: Features
• Harvard Level 1 (L1) memory system with a Memory Management Unit (MMU). • Level 2 (L2) memory system providing cluster memory coherency, optionally including an L2 cache. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 17: Interfaces
• Design for Test (DFT). • Memory Built-In Self Test (MBIST). • Q-channel, for power management. Interfaces on page 2-7 for more information on each of these interfaces. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 18: Implementation Options
• There is no option to implement floating-point without Advanced SIMD. • There is no option to implement the Cryptography Extension without the Advanced SIMD and Floating-point Extension. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 19: Processor Configuration
Either all of the cores have Advanced SIMD and Floating-point Extensions, or none have. • Either all of the cores have Cryptography Extensions, or none have. • All cores must have the same size L1 caches as each other. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 20: Test Features
The Cortex-A53 processor provides test signals that enable the use of both ATPG and MBIST to test the processor and its memory arrays. See Appendix A Signal Descriptions for more information. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 21: Product Documentation And Design Flow
• The processes to sign off the configured design. The ARM product deliverables include reference scripts and information about using them to implement your design. Reference methodology flows supplied by ARM are example reference implementations. Contact your EDA vendor for EDA tool support.
Page 22 Reference to a feature that is included means that the appropriate build and pin configuration options have been selected. Reference to an enabled feature means that the feature has also been configured by software. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 1-11 ID021414 Non-Confidential...
Page 23: Product Revisions
This section describes the differences in functionality between product revisions. r0p0 First release. r0p1 There are no functional changes in this release. r0p2 There are no functional changes in this release. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 1-12 ID021414 Non-Confidential...
Page 24: Functional Description
• About the Cortex-A53 processor functions on page 2-2. • Interfaces on page 2-7. • Clocking and resets on page 2-9. • Power management on page 2-16. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 25: About The Cortex-A53 Processor Functions
The Instruction Fetch Unit (IFU) contains the instruction cache controller and its associated linefill buffer. The Cortex-A53 MPCore instruction cache is 2-way set associative and uses Virtually Indexed Physically Tagged (VIPT) cache lines holding up to 16 A32 instructions, 16 32-bit T32 instructions, 16 A64 instructions, or up to 32 16-bit T32 instructions.
Page 26 The optional Advanced SIMD and Floating-point Extension implements: • ARM NEON technology, a media and signal processing architecture that adds instructions targeted at audio, video, 3-D graphics, image, and speech processing. Advanced SIMD instructions are available in AArch64 and AArch32 states.
Page 27 ® Reference Manual for more information. 2.1.4 Cryptography Extension The optional Cortex-A53 MPCore Cryptography Extension supports the ARMv8 Cryptography Extensions. The Cryptography Extension adds new A64, A32, and T32 instructions to Advanced SIMD that accelerate: • Advanced Encryption Standard (AES) encryption and decryption.
Page 28 L2 requests from the cores. When the Cortex-A53 processor is implemented with a single core, it still includes the Snoop Control Unit (SCU). See Implementation options on page 1-7 for more information. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 29 RAMs. 2.1.9 Debug and trace The Cortex-A53 processor supports a range of debug and trace features including: • ARM v8 debug features in each core. • ETMv4 instruction trace unit for each core. • CoreSight Cross Trigger Interface (CTI).
Page 30: Interfaces
The processor supports dedicated AMBA 4 ATB interfaces for each core that outputs trace information for debugging. The ATB interface is compatible with the CoreSight architecture. See the ARM AMBA 4 ATB Protocol Specification for more information. ® ® ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 31 MBIST interface on page A-32 for information on this interface. 2.2.8 Q-channel The Q-channel interfaces enable communication to an external power controller. See Communication to the Power Management Controller on page 2-26. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 32: Clocking And Resets
APB clock, PCLK and PCLKENDBG, where PCLKENDBG asserts one clock cycle before the rising edge of PCLK. It is important that the relationship between PCLK and PCLKENDBG is maintained. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 33 • If there are any physical effects that could occur while changing the clock frequency, ARM recommends that the clock ratio is changed only while the STANDBYWFIL2 output of the processor is asserted. • The input signal ACLKENM exists in the Cortex-A53 processor if it is configured to include the ACE interface.
Page 34 • If there are any physical effects that could occur while changing the clock frequency, ARM recommends that the clock ratio is changed only while the STANDBYWFIL2 output of the processor is asserted. • The input signal ACLKENS exists in the Cortex-A53 processor if it is configured to include the ACP interface.
Page 35 Functional Description • If there are any physical effects that could occur while changing the clock frequency, ARM recommends that the clock ratio is changed only while the STANDBYWFIL2 output of the processor is asserted. • The input signal SCLKEN exists in the Cortex-A53 processor if it is configured to include the CHI interface.
Page 36 CLREXMONREQ. • CPUQREQn. • CTICHIN. • CTICHOUTACK. • CTIIRQACK. • DBGEN. • EDBGRQ. • EVENTI. • L2FLUSHREQ. • L2QREQn. • NEONQREQn. • NIDEN. • SPIDEN. • SPNIDEN. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 2-13 ID021414 Non-Confidential...
Page 37 Table 2-1 on page 2-15 describes the valid reset signal combinations. All other combinations of reset signals are illegal. In the table, n designates the core that is reset. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 2-14 ID021414 Non-Confidential...
Page 38 No logic is held in reset. nCORERESET[CN:0] all = 1 nPRESETDBG nL2RESET nMBISTRESET a. For cold reset, nCPUPORESET must be asserted. nCORERESET can be asserted, but is not required. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 2-15 ID021414 Non-Confidential...
Page 39: Power Management
This means the Cortex-A53 processor can continue to accept snoops from external devices to access the L2 cache. Figure 2-8 on page 2-17 shows an example of the domains embedded in a System-on-Chip (SoC) power domain. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 2-16 ID021414 Non-Confidential...
Page 40 Logic or RAM retention power only Block is active Caution States not shown in Table 2-4 on page 2-18 Table 2-5 on page 2-18 are unsupported and must not occur. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 2-17 ID021414 Non-Confidential...
Page 41: Normal State
Cortex-A53 processor uses gated clocks and gates to disable inputs to unused functional blocks. Only the logic in use to perform an operation consumes any dynamic power. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 2-18 ID021414 Non-Confidential...
Page 42 STANDBYWFI does not indicate completion of L2 memory system transactions initiated by the processor. All Cortex-A53 processor implementations contain an L2 memory system. This includes implementations without an L2 cache. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 2-19 ID021414 Non-Confidential...
Page 43 An APB access to the debug or trace registers residing in the core power domain. Exit from WFE low-power state occurs when the core detects a reset, the assertion of the EVENTI input signal, or one of the WFE wake up events as described in the ARM Architecture ®...
Page 44 For full shutdown of the Cortex-A53 processor, including implementations with a single core, Cluster shutdown mode without system driven L2 flush on page 2-22 Cluster shutdown mode with system driven L2 flush on page 2-23. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 2-21 ID021414 Non-Confidential...
Page 45 To power down the cluster, apply the following sequence: Ensure all non-lead cores are in shutdown mode, see Individual core shutdown mode on page 2-21. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 2-22 ID021414 Non-Confidential...
Page 46 L2 memory system is idle. All Cortex-A53 processor implementations contain an L2 memory system, including implementations without an L2 cache. Activate the cluster output clamps. Remove power from the PDCORTEXA53 and PDL2 power domains. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 2-23 ID021414 Non-Confidential...
Page 47 Save architectural state, if required. These state saving operations must ensure that the following occur: • All ARM registers, including the CPSR and SPSR, are saved. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 2-24...
Page 48 Continue a normal cold reset sequence with L2RSTDISABLE held HIGH. The architectural state must be restored, if required. Retention state Contact ARM for information about retention state. 2.4.3 Event communication using WFE or SEV An external agent can use the EVENTI pin to participate in a WFE or SEV event communication with the Cortex-A53 processor.
Page 49 L2 cache. Therefore, the power management controller must always wait for assertion of STANDBYWFIL2 before removing power from the Cortex-A53 processor. Figure 2-11 on page 2-27 shows how STANDBYWFI[3:0] and STANDBYWFIL2 correspond to individual cores and the Cortex-A53 processor. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 2-26 ID021414 Non-Confidential...
Page 50 • Optional device capability to deny a quiescence request. • Safe asynchronous interfacing across clock domains. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 2-27 ID021414 Non-Confidential...
Page 51: Chapter 3 Programmers Model
This chapter describes the processor registers and provides information for programming the Cortex-A53 processor. It contains the following sections: • About the programmers model on page 3-2. • ARMv8-A architecture concepts on page 3-4. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 52: About The Programmers Model
Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for ® more information. See the ARM Cortex -A53 MPCore Processor Advanced SIMD and Floating-point Extension ® ® Technical Reference Manual for implementation-specific information. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 53 In the trivial Jazelle implementation, the processor does not accelerate the execution of any bytecodes, and the JVM uses software routines to execute all bytecodes. See the ARM ® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for information.
Page 54: Armv8-A Architecture Concepts
Features 13 32-bit general purpose registers, and a 32-bit PC, SP, and link register (LR). Some of these registers have multiple banked instances for use in different processor modes. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 55 3-8 describes the permitted combinations of Security state and Exception level. Exception terminology This section defines terms used to describe the navigation between exception levels. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 56 When executing at EL3, can access all the system control resources. Non-secure state In Non-secure state, the processor: • Can access only the Non-secure memory address space. • Cannot access the Secure system control resources. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 57 3.2.5 Stack pointer selection Stack pointer behavior depends on the execution state, as follows: AArch64 In EL0, the stack pointer, SP, maps to the SP_EL0 stack pointer register. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 59 This means that, in an implementation where EL3 is using AArch32, the security model is as shown in Figure 3-2 on page 3-10. This figure also shows the expected use of the different exception levels and processor modes. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 60 Thumb instruction set state. 3.2.8 AArch32 execution modes ARMv7 and earlier versions of the ARM architecture define a set of named processor modes, including modes that correspond to different exception types. For compatibility, AArch32 state retains these processor modes.
Page 61 Secure state and the equivalent mode in Non-secure state, the mode name is qualified as Secure or Non-secure. For example, a description of AArch32 operation in EL1 might reference the Secure FIQ mode, or to the Non-secure FIQ mode. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 3-11 ID021414 Non-Confidential...
Page 62: System Control
• AArch64 register summary on page 4-3. • AArch64 register descriptions on page 4-14. • AArch32 register summary on page 4-135. • AArch32 register descriptions on page 4-157. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 63: About System Control
In AArch32 state, the CP15SDISABLE input disables write access to certain system registers. The Cortex-A53 processor does not have any registers that are IMPLEMENTATION DEFINED affected by CP15SDISABLE. For a list of registers affected by CP15SDISABLE, see the ARM Architecture Reference ® Manual ARMv8, for ARMv8-A architecture profile. ARM DDI 0500D Copyright ©...
Page 64: Aarch64 Register Summary
System Control AArch64 register summary This section gives a summary of the system registers in the AArch64 Execution state. For more information on using the system registers, see the ARM Architecture Reference Manual ® ARMv8, for ARMv8-A architecture profile. The following subsections describe the system registers by functional group: •...
Page 65 The reset value depends on the implementation. See the register description for details. h. The value is if the L2 cache is not implemented. 0x09200003 i. The reset value is the value of the Multiprocessor Affinity Register. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 66 Vector Base Address Register, EL1 on page 4-119 ISR_EL1 Interrupt Status Register on page 4-123 VBAR_EL2 Vector Base Address Register, EL2 on page 4-120 VBAR_EL3 Vector Base Address Register, EL3 on page 4-121 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 67 The reset value depends on primary inputs CFGTE, CFGEND and VINITHI. Table 4-3 assumes these signals are LOW. c. See the ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile. ® ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 68 Performance Monitors User Enable Register 0x00000000 PMINTENSET_EL1 Performance Monitors Interrupt Enable Set Register PMINTENCLR_EL1 Performance Monitors Interrupt Enable Clear Register PMOVSSET_EL0 Performance Monitors Overflow Flag Status Set Register ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 69 Description RVBAR_EL3 Reset Vector Base Address Register, EL3 on page 4-121 RMR_EL3 Reset Management Register on page 4-122 0x00000001 a. The reset value depends on the RVBARADDR signal. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 70 Hyp Auxiliary Configuration Register on page 4-74 0x00000000 TTBR0_EL2 Translation Table Base Address Register 0, EL3 TCR_EL2 Translation Control Register, EL2 on page 4-89 VTTBR_EL2 Virtualization Translation Table Base Address Register, EL2 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 71 Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for more information. ® 4.2.9 AArch64 GIC system registers Table 4-9 shows the GIC system registers in AArch64 state. See the ARM Architecture ® Reference Manual ARMv8, for ARMv8-A architecture profile for more information. Table 4-9 GIC system registers...
Page 72 Generic Timer registers. 4.2.11 AArch64 thread registers Table 4-10 shows the thread registers in AArch64 state. See the ARM Architecture Reference ® Manual ARMv8, for ARMv8-A architecture profile for more information about these operations. Table 4-10 AArch64 miscellaneous system control operations...
Page 73 This is the reset value for an ACE interface. For a CHI interface the reset value is 0x80004008 c. Mapped to a 64-bit AArch32 register. d. The reset value depends on the PERIPHBASE signal. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-12 ID021414 Non-Confidential...
Page 74 AArch64 state. Table 4-12 AArch64 address translation register Name Type Reset Width Description PAR_EL1 Physical Address Register, EL1 on page 4-112 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-13 ID021414 Non-Confidential...
Page 75: Aarch64 Register Descriptions
Function [31:24] Implementer Indicates the implementer code. This value is: ASCII character 'A' - implementer is ARM. 0x41 [23:20] Variant Indicates the variant number of the processor. This is the major revision number x in the rx part of the rxpy description of the product revision status.
Page 76 MPIDR_EL1 is a 64-bit register. Figure 4-2 shows the MPIDR_EL1 bit assignments. 40 39 32 31 16 15 Aff3 Aff2 Aff1 Aff0 Figure 4-2 MPIDR_EL1 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-15 ID021414 Non-Confidential...
Page 77 0xFAC 4.3.3 Revision ID Register The REVIDR_EL1 characteristics are: Purpose Provides implementation-specific minor revision information that can be interpreted only in conjunction with the Main ID Register. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-16 ID021414 Non-Confidential...
Page 78 Gives top-level information about the instruction sets supported by the processor in AArch32. Usage constraints This register is accessible as follows: (NS) (SCR.NS = 1) (SCR.NS = 0) ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-17 ID021414 Non-Confidential...
Page 79 Provides information about the programmers model and architecture extensions supported by the processor. Usage constraints This register is accessible as follows: (NS) (SCR.NS = 1) (SCR.NS = 0) ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-18 ID021414 Non-Confidential...
Page 80 Table 4-22 REVIDR access encoding 1111 0000 0001 4.3.6 AArch32 Debug Feature Register 0 The ID_DFR0_EL1 characteristics are: Purpose Provides top level information about the debug system in AArch32. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-19 ID021414 Non-Confidential...
Page 81 Support for ARM trace architecture, with memory-mapped access. In the Trace registers, the ETMIDR gives more information about the implementation. [15:12] CopTrc Indicates support for coprocessor-based trace model: Processor does not support ARM trace architecture with CP14 access. [11:8] Reserved, [7:4] CopSDbg Indicates support for coprocessor-based Secure debug model: Processor supports v8 Debug architecture, with CP14 access.
Page 82 ID_MMFR0_EL1 bit assignments. 28 27 24 23 20 19 16 15 12 11 InnerShr FCSE AuxReg ShareLvl OuterShr PMSA VMSA Figure 4-7 ID_MMFR0_EL1 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-21 ID021414 Non-Confidential...
Page 83 Provides information about the memory model and memory management support in AArch32. Usage constraints This register is accessible as follows: (NS) (SCR.NS = 1) (SCR.NS = 0) ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-22 ID021414 Non-Confidential...
Page 84 None supported. To access the ID_MMFR1_EL1: MRS <Xt>, ID_MMFR1_EL1 ; Read ID_MMFR1_EL1 into Xt Register access is encoded as follows: Table 4-28 ID_MMFR1_EL1 access encoding 0000 0001 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-23 ID021414 Non-Confidential...
Page 85 ID_MMFR2_EL1 bit assignments. 28 27 24 23 20 19 16 15 12 11 HWAccFlg WFIStall MemBarr UniTLB HvdTLB LL1HvdRng L1HvdBG L1HvdFG Figure 4-9 ID_MMFR2_EL1 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-24 ID021414 Non-Confidential...
Page 86 Not supported. To access the ID_MMFR2_EL1: MRS <Xt>, ID_MMFR2_EL1 ; Read ID_MMFR2_EL1 into Xt Register access is encoded as follows: Table 4-30 ID_MMFR2_EL1 access encoding 0000 0001 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-25 ID021414 Non-Confidential...
Page 87 ID_MMFR3_EL1 bit assignments. 28 27 24 23 20 19 16 15 12 11 Supersec CMemSz CohWalk Reserved MaintBcst BPMaint CMaintSW CMaintVA Figure 4-10 ID_MMFR3_EL1 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-26 ID021414 Non-Confidential...
Page 88 MVA operation. To access the ID_MMFR3_EL1: MRS <Xt>, ID_MMFR3_EL1 ; Read ID_MMFR3_EL1 into Xt Register access is encoded as follows: Table 4-32 ID_MMFR3_EL1 access encoding 0000 0001 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-27 ID021414 Non-Confidential...
Page 89 UBFX [7:4] BitCount Indicates the implemented Bit Counting instructions: [3:0] Swap Indicates the implemented Swap instructions in the A32 instruction set: None implemented. To access the ID_ISAR0_EL1: ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-28 ID021414 Non-Confidential...
Page 90 ID_ISAR1_EL1 bit assignments. 28 27 24 23 20 19 16 15 12 11 Jazelle Interwork Immediate IfThen Extend Except_AR Except Endian Figure 4-12 ID_ISAR1_EL1 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-29 ID021414 Non-Confidential...
Page 91 Table 4-36 ID_ISAR1_EL1 access encoding 0000 0010 4.3.14 AArch32 Instruction Set Attribute Register 2 The ID_ISAR2_EL1 characteristics are: Purpose Provides information about the instruction sets implemented by the processor in AArch32. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-30 ID021414 Non-Confidential...
Page 92 ID_ISAR2_EL1 bit assignments. 28 27 24 23 20 19 16 15 12 11 Reversal PSR_AR MultU MultS Mult MemHint LoadStore MultiAccessInt Figure 4-13 ID_ISAR2_EL1 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-31 ID021414 Non-Confidential...
Page 93 STLEX STLEXD To access the ID_ISAR2_EL1: MRS <Xt>, ID_ISAR2_EL1 ; Read ID_ISAR2_EL1 into Xt Register access is encoded as follows: Table 4-38 ID_ISAR2_EL1 access encoding 0000 0010 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-32 ID021414 Non-Confidential...
Page 94 ID_ISAR3_EL1 bit assignments. 28 27 24 23 20 19 16 15 12 11 ThumbEE TrueNOP ThumbCopy SynchPrim SIMD Saturate TabBranch Figure 4-14 ID_ISAR3_EL1 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-33 ID021414 Non-Confidential...
Page 95 Table 4-40 ID_ISAR3_EL1 access encoding 0000 0010 4.3.16 AArch32 Instruction Set Attribute Register 4 The ID_ISAR4_EL1 characteristics are: Purpose Provides information about the instruction sets implemented by the processor in AArch32. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-34 ID021414 Non-Confidential...
Page 96 [3:0] Unpriv Indicates the implemented unprivileged instructions. • , and instructions. LDRBT LDRT STRBT STRT • , and instructions. LDRHT LDRSBT LDRSHT STRHT To access the ID_ISAR4_EL1: ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-35 ID021414 Non-Confidential...
Page 97 Note The optional Advanced SIMD and Floating-point extension is not included in the base product of the processor. ARM requires licensees to have contractual rights to obtain the Advanced SIMD and Floating-point extension. Usage constraints This register is accessible as follows: (NS) (SCR.NS = 1)
Page 98 AArch64. Note The optional Advanced SIMD and Floating-point extension is not included in the base product of the processor. ARM requires licensees to have contractual rights to obtain the Advanced SIMD and Floating-point extension. Usage constraints This register is accessible as follows: (NS) (SCR.NS = 1)
Page 99 The FP and AdvSIMD both take the same value, as both must be implemented, or neither. To access the ID_AA64PFR0_EL1: MRS <Xt>, ID_AA64PFR0_EL1 ; Read ID_AA64PFR0_EL1 into Xt Register access is encoded as follows: Table 4-46 ID_AA64PFR0_EL1 access encoding 0000 0100 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-38 ID021414 Non-Confidential...
Page 100 Performance monitor system registers implemented, PMUv3. 0b0001 [7:4] Tracever Trace extension: Trace system registers not implemented. 0b0000 [3:0] Debugger Debug architecture version: ARMv8-A debug architecture implemented. 0b0110 To access the ID_AA64DFR0_EL1: ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-39 ID021414 Non-Confidential...
Page 101 Note The optional Cryptography engine is not included in the base product of the processor. ARM requires licensees to have contractual rights to obtain the Cortex-A53 Cryptography engine. Usage constraints This register is accessible as follows: (NS) (SCR.NS = 1)
Page 102 Provides information about the implemented memory model and memory management support in the AArch64 Execution state. Usage constraints This register is accessible as follows: (NS) (SCR.NS = 1) (SCR.NS = 0) ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-41 ID021414 Non-Confidential...
Page 103 40 bits, 1 TB. 0b0010 To access the ID_AA64MMFR0_EL1: MRS <Xt>, ID_AA64MMFR0_EL1 ; Read ID_AA64MMFR0_EL1 into Xt Register access is encoded as follows: Table 4-52 ID_AA64MMFR0_EL1 access encoding 0000 0111 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-42 ID021414 Non-Confidential...
Page 104 Indicates the (log (number of words in cache line)) - 2: LineSize 16 words per line. 0b010 a. For more information about encoding, see Table 4-181 on page 4-185. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-43 ID021414 Non-Confidential...
Page 105 CLIDR_EL1 is a 32-bit register. Figure 4-22 shows the CLIDR_EL1 bit assignments. 31 30 29 27 26 24 23 21 20 LoUU LoUIS Ctype3 Ctype2 Ctype1 Figure 4-22 CLIDR_EL1 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-44 ID021414 Non-Confidential...
Page 106 4.3.25 Cache Size Selection Register The CSSELR_EL1 characteristics are: Purpose Selects the current Cache Size ID Register on page 4-183, by specifying: • The required cache level. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-45 ID021414 Non-Confidential...
Page 107 MRS <Xt>, CSSELR_EL1 ; Read CSSELR_EL1 into Xt MSR CSSELR_EL1, <Xt> ; Write Xt to CSSELR_EL1 Register access is encoded as follows: Table 4-58 CSSELR_EL1 access encoding 0000 0001 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-46 ID021414 Non-Confidential...
Page 109 BlockSize Log2 of the block size in words: The block size is 16 words. 0b0100 To access the DCZID_EL0: MRS <Xt>, DCZID_EL0 ; Read DCZID_EL0 into Xt ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-48 ID021414 Non-Confidential...
Page 110 MRS <Xt>, VPIDR_EL2 ; Read VPIDR_EL2 into Xt MSR VPIDR_EL2, <Xt> ; Write Xt to VPIDR_EL2 Register access is encoded as follows: Table 4-64 VPIDR_EL2 access encoding 0000 0000 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-49 ID021414 Non-Confidential...
Page 111 The SCTLR_EL1 characteristics are: Purpose Provides top level control of the system, including its memory system at EL1. SCTLR_EL1 is part of the Virtual memory control registers functional group. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-50 ID021414 Non-Confidential...
Page 112 Figure 4-28 shows the SCTLR_EL1 bit assignments. 24 23 17 16 15 12 11 10 7 6 5 CP15BEN nTWE THEE nTWI Figure 4-28 SCTLR_EL1 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-51 ID021414 Non-Confidential...
Page 113 Disables execution access to the DC ZVA instruction at EL0. The instruction is trapped to EL1. This is the reset value. Enables execution access to the DC ZVA instruction at EL0. [13] Reserved, ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-52 ID021414 Non-Confidential...
Page 114 Table 4-67 SCTLR_EL1 bit assignments (continued) Bits Name Function [12] Instruction cache enable. The possible values are: Instruction caches disabled. This is the reset value. Instruction caches enabled. [11] Reserved, [10] Reserved, ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-53 ID021414 Non-Confidential...
Page 115 Data and unified caches disabled. This is the reset value. Data and unified caches enabled. Alignment check enable. The possible values are: Alignment fault checking disabled. This is the reset value. Alignment fault checking enabled. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-54 ID021414 Non-Confidential...
Page 116 Figure 4-29 shows the ACTLR_EL2 bit assignments. L2ACTLR_EL1 access control L2ECTLR_EL1 access control L2CTLR_EL1 access control CPUECTLR_EL1 access control CPUACTLR_EL1 access control Figure 4-29 ACTLR_EL2 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-55 ID021414 Non-Confidential...
Page 117 (SCR.NS = 1) (SCR.NS = 0) Configurations ACTLR_EL3 is mapped to AArch32 register ACTLR (S). See Auxiliary Control Register on page 4-196. Attributes ACTLR_EL3 is a 32-bit register. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-56 ID021414 Non-Confidential...
Page 118 4.3.34 Architectural Feature Access Control Register The CPACR_EL1 characteristics are: Purpose Controls access to trace functionality and access to registers associated with Advanced SIMD and Floating-point execution. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-57 ID021414 Non-Confidential...
Page 119 MSR CPACR_EL1, <Xt> ; Write Xt to CPACR_EL1 4.3.35 System Control Register, EL2 The SCTLR_EL2 characteristics are: Purpose Provides top level control of the system, including its memory system at EL2. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-58 ID021414 Non-Confidential...
Page 120 Force treatment of all memory regions with write permissions as XN. The possible values are: Regions with write permissions are not forced XN. This is the reset value. Regions with write permissions are forced XN. [18] Reserved, [17] Reserved, ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-59 ID021414 Non-Confidential...
Page 121 Usage constraints This register is accessible as follows: (NS) (SCR.NS = 1) (SCR.NS = 0) Configurations HCR_EL2[31:0] is architecturally mapped to AArch32 register HCR. See Hyp Configuration Register on page 4-211. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-60 ID021414 Non-Confidential...
Page 122 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 10 9 8 7 6 5 4 3 SWIO TRVM TTLB TACR TIDCP TID0 TID3 TID1 TID2 Figure 4-33 HCR_EL2 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-61 ID021414 Non-Confidential...
Page 123 The possible values are: Non-secure EL1 TLB maintenance instructions are not trapped. This is the reset value. TLB maintenance instructions executed from Non-secure EL1that are not UNDEFINED trapped to EL2. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-62 ID021414 Non-Confidential...
Page 124 ID group 0 register accesses are not trapped. This is the reset value. Reads to ID group 0 registers executed from Non-secure EL1 are trapped to EL2. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-63 ID021414 Non-Confidential...
Page 125 0b10 Full system. 0b11 This value is combined with the specified level of the barrier held in its instruction, according to the algorithm for combining shareability attributes. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-64 ID021414 Non-Confidential...
Page 126 Enables second stage of translation. The possible values are: Disables second stage translation. This is the reset value. Enables second stage translation for execution in Non-secure EL1 and EL0. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-65 ID021414 Non-Confidential...
Page 127 MDCR_EL2 is a 32-bit register. Figure 4-34 shows the MDCR_EL2 bit assignments. 11 10 9 8 7 6 5 4 HPMN TPMCR HPME TDOSA TDRA Figure 4-34 MDCR_EL2 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-66 ID021414 Non-Confidential...
Page 129 Has no effect on performance monitor accesses. Trap Non-secure EL0 and EL1 accesses to Performance Monitors registers that are not to EL2. UNALLOCATED This bit resets to 0. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-68 ID021414 Non-Confidential...
Page 130 CPTR_EL2 is architecturally mapped to AArch32 register HCPTR. See Hyp Architectural Feature Trap Register on page 4-221. Attributes CPTR_EL2 is a 32-bit register. Figure 4-35 on page 4-70 shows the CPTR_EL2 bit assignments. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-69 ID021414 Non-Confidential...
Page 131 Usage constraints This register is accessible as follows: (NS) (SCR.NS = 1) (SCR.NS = 0) Configurations HSTR_EL2 is architecturally mapped to AArch32 register HSTR. See Hyp System Trap Register on page 4-236. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-70 ID021414 Non-Confidential...
Page 132 System Control Attributes HSTR_EL2 is a 32-bit register. Figure 4-36 shows the HSTR_EL2 bit assignments. TTEE Figure 4-36 HSTR_EL2 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-71 ID021414 Non-Confidential...
Page 133 Has no effect on Non-secure accesses to CP15 registers. Trap valid Non-secure accesses to coprocessor primary register CRn = 10 to Hyp mode. The reset value is 0. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-72 ID021414 Non-Confidential...
Page 134 Trap valid Non-secure accesses to coprocessor primary register CRn = 0 to Hyp mode. The reset value is 0. To access the HSTR_EL2: MRS <Xt>, HSTR_EL2 ; Read HSTR_EL2 into Xt MSR HSTR_EL2, <Xt> ; Write Xt to HSTR_EL2 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-73 ID021414 Non-Confidential...
Page 136 Disables alignment fault checking. This is the reset value. Enables alignment fault checking. Global enable for the EL3 MMU. The possible values are: Disables EL3 MMU. This is the reset value. Enables EL3 MMU. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-75 ID021414 Non-Confidential...
Page 137 SCR_EL3 is a 32-bit register. Figure 4-38 shows the SCR_EL3 bit assignments. 10 9 8 7 6 4 3 2 1 0 Figure 4-38 SCR_EL3 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-76 ID021414 Non-Confidential...
Page 138 Enable Secure EL1 access to CNTPS_TVAL_EL1, CNTS_CTL_EL1, and CNTPS_CVAL_EL1 registers. The possible values are: Registers accessible only in EL3. This is the reset value. Registers accessible in EL3 and EL1 when SCR_EL3.NS is 0. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-77 ID021414 Non-Confidential...
Page 139 Secure Debug Enable Register The SDER32_EL3 characteristics are: Purpose Allows access to the AArch32 register SDER only from AArch64 state. Its value has no effect on execution in AArch64 state. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-78 ID021414 Non-Confidential...
Page 140 This is one of the translation tables for the stage 1 translation of memory accesses from modes other than Hyp mode. Usage constraints This register is accessible as follows: (NS) (SCR.NS = 1) (SCR.NS = 0) ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-79 ID021414 Non-Confidential...
Page 141 Translation table base address, bits[47:x]. Bits [x-1:0] are x is based on the value of TCR_EL1.T0SZ, the stage of translation, and the memory translation granule size. For instructions on how to calculate it, see the ARM Architecture Reference Manual ARMv8, for ®...
Page 142 Translation table base address, bits[47:x]. Bits [x-1:0] are x is based on the value of TCR_EL1.T0SZ, the stage of translation, and the memory translation granule size. For instructions on how to calculate it, see the ARM Architecture Reference Manual ARMv8, for ®...
Page 143 Usage constraints This register is accessible as follows: (NS) (SCR.NS = 1) (SCR.NS = 0) Configurations MDCR_EL3 is mapped to AArch32 register SDCR. See Secure Debug Control Register on page 4-204. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-82 ID021414 Non-Confidential...
Page 144 MDCR_EL3 is a 32-bit register. Figure 4-43 shows the MDCR_EL3 bit assignments. 20 19 16 15 14 13 11 10 9 EPMAD SPD32 EDAD TDOSA SPME Figure 4-43 MDCR_EL3 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-83 ID021414 Non-Confidential...
Page 145 Access to breakpoint and watchpoint registers from external debugger is permitted. Access to breakpoint and watchpoint registers from external debugger is disabled, unless overridden by authentication interface. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-84 ID021414 Non-Confidential...
Page 146 UNKNOWN [5:0] Reserved, To access the MDCR_EL3: MRS <Xt>, MDCR_EL3 ; Read EL3 Monitor Debug Configuration Register MSR MDCR_EL3, <Xt> ; Write EL3 Monitor Debug Configuration Register ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-85 ID021414 Non-Confidential...
Page 147 26 25 24 23 22 16 15 14 13 11 10 9 TG1 SH1 T1SZ T0SZ ORGN1 Reserved IRGN1 EPD0 TBI0 EPD1 IRGN0 TBI1 ORGN0 Figure 4-44 TCR_EL1 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-86 ID021414 Non-Confidential...
Page 148 Normal memory, Outer Non-cacheable. 0b00 Normal memory, Outer Write-Back Write-Allocate Cacheable. 0b01 Normal memory, Outer Write-Through Cacheable. 0b10 Normal memory, Outer Write-Back no Write-Allocate Cacheable. 0b11 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-87 ID021414 Non-Confidential...
Page 149 Size offset of the memory region addressed by TTBR0_EL1. The region size is 2 (64-T0SZ) bytes. To access the TCR_EL1: MRS <Xt>, TCR_EL1 ; Read TCR_EL1 into Xt MSR TCR_EL1, <Xt> ; Write Xt to TCR_EL1 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-88 ID021414 Non-Confidential...
Page 150 24 23 22 21 20 19 18 16 15 14 13 12 11 10 9 8 7 6 5 T0SZ IRGN0 ORGN0 Figure 4-45 TCR_EL2 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-89 ID021414 Non-Confidential...
Page 151 Normal memory, Inner Write-Back no Write-Allocate Cacheable. 0b11 [7:6] Reserved, [5:0] T0SZ (64-T0SZ) Size offset of the memory region addressed by TTBR0_EL2. The region size is 2 bytes. To access the TCR_EL2: ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-90 ID021414 Non-Confidential...
Page 152 Virtualization Translation Control Register on page 4-233. Attributes VTCR_EL2 is a 32-bit register. Figure 4-46 shows the VTCR_EL2 bit assignments. T0SZ ORGN0 IRGN0 Figure 4-46 VTCR_EL2 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-91 ID021414 Non-Confidential...
Page 153: Domain Access Control Register
Domain Access Control Register The DACR32_EL2 characteristics are: Purpose Allows access to the AArch32 DACR register from AArch64 state only. Its value has no effect on execution in AArch64 state. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-92 ID021414 Non-Confidential...
Page 154 TTBR0_EL3 is mapped to AArch32 register TTBR0 (S). See Translation Table Base Register 0 on page 4-224. Attributes TTBR0_EL3 is a 64-bit register. Figure 4-48 on page 4-94 shows the TTBR0_EL3 bit assignments. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-93 ID021414 Non-Confidential...
Page 155 Translation table base address, bits[47:x]. Bits [x-1:0] are x is based on the value of TCR_EL1.T0SZ, the stage of translation, and the memory translation granule size. For instructions on how to calculate it, see the ARM Architecture Reference Manual ARMv8, for ®...
Page 156 Figure 4-49 TCR_EL3 bit assignments Table 4-88 shows the TCR_EL3 bit assignments. Table 4-88 TCR_EL3 bit assignments Bits Name Function [63:32] Reserved, [31] Reserved, [30:24] Reserved, [23] Reserved, ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-95 ID021414 Non-Confidential...
Page 157 Size offset of the memory region addressed by TTBR0_EL3. The region size is 2 (64-T0SZ) bytes. To access the TCR_EL3: MRS <Xt>, TCR_EL3 ; Read EL3 Translation Control Register MRS TCR_EL3, <Xt> ; Read EL3 Translation Control Register ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-96 ID021414 Non-Confidential...
Page 158 Data Fault Status Register on page 4-239. Attributes ESR_EL1 is a 32-bit register. Figure 4-50 shows the ESR_EL1 bit assignments. 25 24 ISS Valid Figure 4-50 ESR_EL1 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-97 ID021414 Non-Confidential...
Page 159 IFSR when using the Long-descriptor translation table format on page 4-244. IFSR32_EL2 when using the Short-descriptor translation table format Figure 4-51 on page 4-99 shows the IFSR32_EL2 bit assignments when using the Short-descriptor translation table format. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-98 ID021414 Non-Confidential...
Page 160 Synchronous parity error on translation table walk, second level. 0b11110 IFSR32_EL2 when using the Long-descriptor translation table format Figure 4-52 on page 4-100 shows the IFSR32_EL2 bit assignments when using the Long-descriptor translation table format. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-99 ID021414 Non-Confidential...
Page 161 LL bits in the Status field encode the lookup level associated with the MMU fault. Table 4-92 Encodings of LL bits associated with the MMU fault Bits Meaning Reserved 0b00 Level 1 0b01 Level 2 0b10 Level 3 0b11 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-100 ID021414 Non-Confidential...
Page 162 ESR_EL2 is architecturally mapped to AArch32 register HSR. See Syndrome Register on page 4-246. Attributes ESR_EL2 is a 32-bit register. Figure 4-53 shows the ESR_EL2 bit assignments. 26 25 24 Figure 4-53 ESR_EL2 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-101 ID021414 Non-Confidential...
Page 163 Data Fault Status Register on page 4-239. Attributes ESR_EL3 is a 32-bit register. Figure 4-54 shows the ESR_EL3 bit assignments. 25 24 ISS Valid Figure 4-54 ESR_EL3 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-102 ID021414 Non-Confidential...
Page 164 (NS). See Instruction Fault Address Register on page 4-248. Attributes FAR_EL1 is a 64-bit register. Figure 4-55 shows the FAR_EL1 bit assignments. Figure 4-55 FAR_EL1 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-103 ID021414 Non-Confidential...
Page 165 IFAR (S). See Instruction Fault Address Register on page 4-248. Attributes FAR_EL2 is a 64-bit register. Figure 4-56 shows the FAR_EL2 bit assignments. Figure 4-56 FAR_EL2 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-104 ID021414 Non-Confidential...
Page 166 Bits [47:12] of the faulting intermediate physical address. The equivalent upper bits in this field are [3:0] Reserved, To access the HPFAR_EL: MRS <Xt>, HPFAR_EL2 ; Read EL2 Fault Address Register MSR HPFAR_EL2, <Xt> ; Write EL2 Fault Address Register ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-105 ID021414 Non-Confidential...
Page 167 Number of cores L2 Data RAM input latency Reserved SCU- L2 cache protection Reserved CPU Cache Protection L2 Data RAM output latency Figure 4-58 L2CTLR_EL1 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-106 ID021414 Non-Confidential...
Page 168 The L2ECTLR_EL1 characteristics are: Purpose Provides additional control options for the L2 IMPLEMENTATION DEFINED memory system. This register is used for dynamically changing, but implementation specific, control bits. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-107 ID021414 Non-Confidential...
Page 169 Figure 4-59 shows the L2ECTLR_EL1 bit assignments. AXI or AMBA 5 CHI asynchronous error L2 dynamic retention control L2 internal asynchronous error Figure 4-59 L2ECTLR_EL1 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-108 ID021414 Non-Confidential...
Page 170 • This register can be written only when the L2 memory system is idle. ARM recommends that you write to this register after a powerup reset before the MMU is enabled and before any ACE, CHI or ACP traffic has begun.
Page 171 31 30 29 15 14 13 4 3 2 L2 Victim Control Enable UniqueClean evictions with data Disable clean/evict push to external Figure 4-60 L2ACTLR_EL1 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-110 ID021414 Non-Confidential...
Page 172 (SCR.NS = 0) Configurations There is no additional configuration data for FAR_EL3. Attributes FAR_EL3 is a 64-bit register. Figure 4-61 on page 4-112 shows the FAR_EL3 bit assignments. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-111 ID021414 Non-Confidential...
Page 173 PAR_EL1 bit assignments when the Virtual Address to Physical Address conversion completes successfully. 56 55 48 47 12 11 10 9 8 AttrH AttrL Figure 4-62 PAR_EL1 pass bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-112 ID021414 Non-Confidential...
Page 174 System Control Table 4-103 on page 4-114 shows the PAR_EL1 bit assignments when the Virtual Address to Physical Address conversion completes successfully. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-113 ID021414 Non-Confidential...
Page 175 [10] Reserved, Non-secure. The NS attribute for a translation table entry read from Secure state. This bit is for a translation table entry from Non-secure state. UNKNOWN ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-114 ID021414 Non-Confidential...
Page 176 Figure 4-63 shows the PAR_EL1 bit assignments when the Virtual Address to Physical Address conversion is aborted. 10 9 8 7 6 Figure 4-63 PAR_El1 fail bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-115 ID021414 Non-Confidential...
Page 177 Translation aborted because of a stage 2 fault during a stage 1 table walk. Reserved, [6:1] Fault status code, as shown in the Data Abort ESR encoding. See the ARM Architecture Reference Manual ® ARMv8, for ARMv8-A architecture profile for more information.
Page 178 , RW not Normal Memory, Inner Write-through non-transient UNPREDICTABLE 0b10RW Device-GRE memory Normal Memory, Inner Write-back non-transient (RW=00) 0b1100 , RW not Normal Memory, Inner Write-back non-transient UNPREDICTABLE 0b11RW ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-117 ID021414 Non-Confidential...
Page 179 The MAIR_EL3 characteristics are: Purpose Provides the memory attribute encodings corresponding to the possible AttrIndx values in a Long-descriptor format translation table entry for stage 1 translations at EL3. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-118 ID021414 Non-Confidential...
Page 180 Vector Base Address Register on page 4-263. Attributes VBAR_EL1 is a 64-bit register. Figure 4-65 shows the VBAR_EL1 bit assignments. 11 10 Vector base address Figure 4-65 VBAR_EL1 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-119 ID021414 Non-Confidential...
Page 181 Base address of the exception vectors for exceptions taken in this exception level. [10:0] Reserved, To access the VBAR_EL2: MRS <Xt>, VBAR_EL2 ; Read VBAR_EL2 into Xt MSR VBAR_EL2, <Xt> ; Write Xt to VBAR_EL2 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-120 ID021414 Non-Confidential...
Page 182 The RVBAR_EL3 characteristics are: Purpose Contains the address that execution starts from after reset when executing in the AArch64 state. RVBAR_EL3 is part of the Reset management registers functional group. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-121 ID021414 Non-Confidential...
Page 183 Configurations The RMR_EL3 is architecturally mapped to the AArch32 RMR register. Attributes RMR_EL3 is a 32-bit register. Figure 4-69 on page 4-123 shows the RMR_EL3 bit assignments. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-122 ID021414 Non-Confidential...
Page 184: Interrupt Status Register
ISR_EL1 is architecturally mapped to AArch32 register ISR. See Interrupt Status Register on page 4-265. Attributes ISR_EL1 is a 32-bit register. Figure 4-70 on page 4-124 shows the ISR_EL1 bit assignments. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-123 ID021414 Non-Confidential...
Page 185 There is one 64-bit CPU Auxiliary Control Register for each core in the cluster. Usage constraints This register is accessible as follows: (NS) (SCR.NS = 1) (SCR.NS = 0) ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-124 ID021414 Non-Confidential...
Page 186 System Control The CPU Auxiliary Control Register can be written only when the system is idle. ARM recommends that you write to this register after a powerup reset, before the MMU is enabled, and before any ACE or ACP traffic begins.
Page 187 Disable ReadUnique request for prefetch streams initiated by STB accesses: ReadUnique used for prefetch streams initiated from STB accesses. This is the reset value. ReadShared used for prefetch streams initiated from STB accesses. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-126 ID021414 Non-Confidential...
Page 188 Disable optimized Data Memory Barrier behavior. [9:0] Reserved, To access the CPUACTLR_EL1: MRS <Xt>, S3_1_C15_C2_0 ; Read EL1 CPU Auxiliary Control Register MSR S3_1_C15_C2_0, <Xt> ; Write EL1 CPU Auxiliary Control Register ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-127 ID021414 Non-Confidential...
Page 189 CPUECTLR_EL1 is a 64-bit register. Figure 4-72 shows the CPUECTLR_EL1 bit assignments. 7 6 5 SMPEN Advanced-SIMD/FP retention control CPU retention control Figure 4-72 CPUECTLR_EL1 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-128 ID021414 Non-Confidential...
Page 190 • L1 data RAMs. • L1 tag RAMs. • L1 dirty RAMs. • TLB RAMs. This register is used for recording ECC errors on all processor RAMs. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-129 ID021414 Non-Confidential...
Page 191 40 39 24 23 21 20 18 17 12 11 Other error Repeat error RAMID RAM address count count Fatal Valid CPUID/Way Figure 4-73 CPUMERRSR_EL1 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-130 ID021414 Non-Confidential...
Page 192 Indicates the index address of the first memory error. Note • A fatal error results in the RAMID, Way, and RAM address recording the fatal error, even if the sticky bit is set. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-131 ID021414 Non-Confidential...
Page 193 L2MERRSR_EL1 bit assignments. 40 39 24 23 22 21 18 17 Other error Repeat error RAMID RAM address count count Fatal Valid CPUID/Way Figure 4-74 L2MERRSR_EL1 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-132 ID021414 Non-Confidential...
Page 194 If two or more first memory error events from different RAMs occur in the same cycle, one of the errors is selected arbitrarily, while the Other error count field is incremented only by one. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-133 ID021414 Non-Confidential...
Page 195 Name Function [63:40] Reserved, [39:18] PERIPHBASE[39:18] The input PERIPHBASE[39:18] determines the reset value. [17:0] Reserved, To access the CBAR_EL1: MRS <Xt>, S3_1_C15_C3_0 ; Read CBAR_EL1 into Xt ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-134 ID021414 Non-Confidential...
Page 196: Aarch32 Register Summary
In AArch32 state you access the system registers through a conceptual coprocessor, identified as CP15, the System Control Coprocessor. Within CP15, there is a top-level grouping of system registers by a primary coprocessor register number, c0-c15. See the ARM Architecture ®...
Page 197 The name of the register or operation. Some assemblers support aliases that you can use to access the registers and operations by name. Reset Reset value of register. Description Cross-reference to the register description. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-136 ID021414 Non-Confidential...
Page 198 Bits [31:28] are if the GIC CPU interface is enabled, otherwise. and 0x0 c. ID_ISAR5 has the value if the Cryptography Extension is not implemented and enabled. 0x00010001 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-137 ID021414 Non-Confidential...
Page 199 The reset value depends on the FPU and NEON configuration. If Advanced SIMD and Floating-point are implemented, the reset value is . If Advanced SIMD and Floating-point are not implemented, the reset value is 0x000033FF 0x0000BFFF ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-138 ID021414 Non-Confidential...
Page 200 32-bit wide system registers you can access when the processor is in AArch32 state and the value of CRn is c4. Table 4-126 c3 register summary Name Reset Description ICC_PMR Priority Mask Register 0x00000000 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-139 ID021414 Non-Confidential...
Page 201 Table 4-129 shows the 32-bit wide system registers you can access when the processor is in AArch32 state and the value of CRn is c7. See the ARM Architecture Reference Manual ® ARMv8, for ARMv8-A architecture profile for more information.
Page 202 Table 4-130 shows the 32-bit wide system registers you can access when the processor is in AArch32 state and the value of CRn is c9. See the ARM Architecture Reference Manual ® ARMv8, for ARMv8-A architecture profile for more information.
Page 203 Reset Description VBAR Vector Base Address Register on page 4-263. 0x00000000 MVBAR Monitor Vector Base Address Register. See the ARM ® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for more information. Reset Management Register on page 4-264. 0x00000000 Interrupt Status Register on page 4-265.
Page 204 Interrupt Controller List Register 3 0x00000000 ICC_MCTLR Interrupt Control Register for EL3 0x00000400 ICC_MSRE System Register Enable Register for EL3 0x00000000 ICC_MGRPEN1 Interrupt Controller Monitor Interrupt Group 1 Enable 0x00000000 register ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-143 ID021414 Non-Confidential...
Page 205 4.4.14 c14 registers Table 4-134 shows the CP15 system registers when the processor is in AArch32 state and the value of CRn is c14. See the ARM Architecture Reference Manual ARMv8, for ARMv8-A ® architecture profile for more information. Table 4-134 c14 register summary...
Page 206 The reset value for bits[9:8, 2:0] is 0b00000 b. The reset value for bit[0] is 0. c. The reset value for bit[2] is 0 and for bits[1:0] is 0b11 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-145 ID021414 Non-Confidential...
Page 207 This is the reset value for an ACE interface. For a CHI interface the reset value is 0x80004008 b. The reset value depends on the processor configuration. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-146 ID021414 Non-Confidential...
Page 208 CPUECTLR CPU Extended Control Register on page 4-271 0x0000000000000000 CPUMERRSR CPU Memory Error Syndrome Register on page 4-273 L2MERRSR L2 Memory Error Syndrome Register on page 4-276 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-147 ID021414 Non-Confidential...
Page 209 ID_ISAR5 has the value if the Cryptography Extension is not implemented and enabled. 0x00010001 d. The value is if the L2 cache is not implemented. 0x09200003 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-148 ID021414 Non-Confidential...
Page 210 Description SCTLR 32 bit System Control Register on page 4-191 0x00C50838 TTBR0 32 bit Translation Table Base Register 0, see the ARM ® Architecture Reference Manual ARMv8, for ARMv8-A 64 bit architecture profile TTBR1 32 bit Translation Table Base Register 1, see the ARM ®...
Page 211 FCSE Process ID Register on page 4-267 0x00000000 4.4.21 AArch32 Address registers Table 4-141 shows the address translation register and operations. See the ARM Architecture ® Reference Manual ARMv8, for ARMv8-A architecture profile for more information. Table 4-141 Address translation operations...
Page 212 EL1 only Thread ID Register HTPIDR Hyp Software Thread ID Register 4.4.23 AArch32 Performance monitor registers Table 4-143 shows the performance monitor registers. See the ARM Architecture Reference ® Manual ARMv8, for ARMv8-A architecture profile for more information. Table 4-143 Performance monitor registers Name...
Page 213 The reset value is if L2 cache is not implemented. 0x623FFFFF 4.4.24 AArch32 Secure registers Table 4-144 shows the Secure registers. See the ARM Architecture Reference Manual ARMv8, ® for ARMv8-A architecture profile for more information. Table 4-144 Security registers Name...
Page 214 System Control 4.4.25 AArch32 Virtualization registers Table 4-145 shows the Virtualization registers. See the ARM Architecture Reference Manual ® ARMv8, for ARMv8-A architecture profile for more information. Table 4-145 Virtualization registers Name Reset Width Description VPIDR 32-bit Virtualization Processor ID Register on page 4-189...
Page 215 System Register Enable Register for 0x00000000 ICH_HCR 32-bit Interrupt Controller Hyp Control 0x00000000 Register ICH_VTR 32-bit Interrupt Controller VGIC Type 0x90000003 Register ICH_MISR 32-bit Interrupt Controller Maintenance 0x00000000 Interrupt State Register ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-154 ID021414 Non-Confidential...
Page 216 This is the reset value in non-secure state. In secure state, the reset value is 0x00000002. 4.4.27 AArch32 Generic Timer registers Chapter 10 Generic Timer for information on the timer registers. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-155 ID021414 Non-Confidential...
Page 217 This is the reset value for an ACE interface. For a CHI interface the reset value is 0x80004008 c. See Direct access to internal memory on page 6-13 for information on how these registers are used. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-156 ID021414 Non-Confidential...
Page 218: Aarch32 Register Descriptions
Function [31:24] Implementer Indicates the implementer code. This value is: ASCII character 'A' - implementer is ARM Limited. 0x41 [23:20] Variant Indicates the variant number of the processor. This is the major revision number n in the rn part of the rnpn description of the product revision status.
Page 219 MPIDR is a 32-bit register. Figure 4-77 shows the MPIDR bit assignments. 31 30 29 25 24 16 15 Aff2 Aff1 Aff0 Figure 4-77 MPIDR bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-158 ID021414 Non-Confidential...
Page 220 Provides implementation-specific minor revision information that can be interpreted only in conjunction with the Main ID Register. Usage constraints This register is accessible as follows: (NS) (NS) (SCR.NS = 1) (SCR.NS = 0) ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-159 ID021414 Non-Confidential...
Page 221 The processor does not implement the features described by the TLBTR, so this register is always RAZ. 4.5.6 Processor Feature Register 0 The ID_PFR0 characteristics are: Purpose Gives top-level information about the instruction sets supported by the processor in AArch32. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-160 ID021414 Non-Confidential...
Page 222 To access the ID_PFR0: MRC p15,0,<Rt>,c0,c1,0 ; Read ID_PFR0 into Rt Register access is encoded as follows: Table 4-155 ID_PFR0 access encoding coproc opc1 opc2 1111 0000 0001 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-161 ID021414 Non-Confidential...
Page 223 ID_PFR1 is a 32-bit register. Figure 4-80 shows the ID_PFR1 bit assignments. 20 19 16 15 12 11 GIC CPU Reserved GenTimer MProgMod Security ProgMod Virtualization Figure 4-80 ID_PFR1 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-162 ID021414 Non-Confidential...
Page 224 ID_DFR0 is architecturally mapped to AArch64 register ID_DFR0_EL1. AArch32 Debug Feature Register 0 on page 4-19. There is one copy of this register that is used in both Secure and Non-secure states. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-163 ID021414 Non-Confidential...
Page 225 Support for ARM trace architecture, with memory-mapped access. In the Trace registers, the ETMIDR gives more information about the implementation. [15:12] CopTrc Indicates support for coprocessor-based trace model: Processor does not support ARM trace architecture, with CP14 access. [11:8] Reserved, RAZ. [7:4] CopSDbg Indicates support for coprocessor-based Secure debug model: Processor supports v8 Debug architecture, with CP14 access.
Page 226 ID_MMFR0 bit assignments. 28 27 24 23 20 19 16 15 12 11 InnerShr FCSE AuxReg ShareLvl OuterShr PMSA VMSA Figure 4-82 ID_MMFR0 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-165 ID021414 Non-Confidential...
Page 227 Provides information about the memory model and memory management support in AArch32. Usage constraints This register is accessible as follows: (NS) (NS) (SCR.NS = 1) (SCR.NS = 0) ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-166 ID021414 Non-Confidential...
Page 228 Indicates the supported L1 cache line maintenance operations by MVA, for a Harvard cache implementation: None supported. To access the ID_MMFR1: MRC p15, 0, <Rt>, c0, c1, 5; Read ID_MMFR1 into Rt ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-167 ID021414 Non-Confidential...
Page 229 ID_MMFR2 bit assignments. 28 27 24 23 20 19 16 15 12 11 HWAccFlg WFIStall MemBarr UniTLB HvdTLB LL1HvdRng L1HvdBG L1HvdFG Figure 4-84 ID_MMFR2 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-168 ID021414 Non-Confidential...
Page 230 To access the ID_MMFR2: MRC p15,0,<Rt>,c0,c1,6 ; Read ID_MMFR2 into Rt Register access is encoded as follows: Table 4-165 ID_MMFR2 access encoding coproc opc1 opc2 1111 0000 0001 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-169 ID021414 Non-Confidential...
Page 231 ID_MMFR3 bit assignments. 28 27 24 23 20 19 16 15 12 11 Supersec CMemSz CohWalk Reserved MaintBcst BPMaint CMaintSW CMaintVA Figure 4-85 ID_MMFR3 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-170 ID021414 Non-Confidential...
Page 232 MRC p15, 0, <Rt>, c0, c1, 7; Read ID_MMFR3 into Rt Register access is encoded as follows: Table 4-167 ID_MMFR3 access encoding coproc opc1 opc2 1111 0000 0001 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-171 ID021414 Non-Confidential...
Page 233 ID_ISAR0 bit assignments. 28 27 24 23 20 19 16 15 12 11 Divide Debug Coproc CmpBranch Bitfield BitCount Swap Figure 4-86 ID_ISAR0 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-172 ID021414 Non-Confidential...
Page 234 Provides information about the instruction sets implemented by the processor in AArch32. Usage constraints This register is accessible as follows: (NS) (NS) (SCR.NS = 1) (SCR.NS = 0) ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-173 ID021414 Non-Confidential...
Page 235 ID_ISAR1 bit assignments. 28 27 24 23 20 19 16 15 12 11 Jazelle Interwork Immediate IfThen Extend Except_AR Except Endian Figure 4-87 ID_ISAR1 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-174 ID021414 Non-Confidential...
Page 236 1111 0000 0010 4.5.16 Instruction Set Attribute Register 2 The ID_ISAR2 characteristics are: Purpose Provides information about the instruction sets implemented by the processor in AArch32. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-175 ID021414 Non-Confidential...
Page 237 ID_ISAR2 bit assignments. 28 27 24 23 20 19 16 15 12 11 Reversal PSR_AR MultU MultS Mult MemHint LoadStore MultiAccessInt Figure 4-88 ID_ISAR2 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-176 ID021414 Non-Confidential...
Page 238 LDAEXD , and ) instructions. STLB STLH STLEXB STLEXH STLEX STLEXD To access the ID_ISAR2: MRC p15, 0, <Rt>, c0, c2, 2 ; Read ID_ISAR2 into Rt ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-177 ID021414 Non-Confidential...
Page 239 ID_ISAR3 bit assignments. 28 27 24 23 20 19 16 15 12 11 ThumbEE TrueNOP ThumbCopy SynchPrim SIMD Saturate TabBranch Figure 4-89 ID_ISAR3 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-178 ID021414 Non-Confidential...
Page 240 1111 0000 0010 4.5.18 Instruction Set Attribute Register 4 The ID_ISAR4 characteristics are: Purpose Provides information about the instruction sets implemented by the processor in AArch32. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-179 ID021414 Non-Confidential...
Page 241 ID_ISAR4 bit assignments. 28 27 24 23 20 19 16 15 12 11 SWP_frac PSR_M Barrier Writeback WithShifts Unpriv SynchPrim_frac Figure 4-90 ID_ISAR4 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-180 ID021414 Non-Confidential...
Page 242 1111 0000 0010 4.5.19 Instruction Set Attribute Register 5 The ID_ISAR5 characteristics are: Purpose Provides information about the instruction sets that the processor implements. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-181 ID021414 Non-Confidential...
Page 243 ID_ISAR5 is a 32-bit register. Figure 4-91 shows the ID_ISAR5 bit assignments. 20 19 16 15 12 11 CRC32 SHA2 SHA1 SEVL Figure 4-91 ID_ISAR5 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-182 ID021414 Non-Confidential...
Page 244 The CCSIDR characteristics are: Purpose Provides information about the architecture of the caches. Usage constraints This register is accessible as follows: (NS) (NS) (SCR.NS = 1) (SCR.NS = 0) ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-183 ID021414 Non-Confidential...
Page 245 Indicates the (log (number of words in cache line)) - 2: LineSize 16 words per line. 0b010 a. For more information about encoding, see Table 4-181 on page 4-185. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-184 ID021414 Non-Confidential...
Page 246 The CLIDR characteristics are: Purpose Identifies: • The type of cache, or caches, implemented at each level. • The Level of Coherency and Level of Unification for the cache hierarchy. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-185 ID021414 Non-Confidential...
Page 247 So, for example, if Ctype2 is the first Cache Type field with a value of , the value of Ctype3 must be ignored. 0b000 To access the CLIDR: ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-186 ID021414 Non-Confidential...
Page 248 There are separate Secure and Non-secure copies of this register. Attributes CSSELR is a 32-bit register. Figure 4-94 shows the CSSELR bit assignments. UNK/SBZP Level Figure 4-94 CSSELR bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-187 ID021414 Non-Confidential...
Page 249 There is one copy of this register that is used in both Secure and Non-secure states. Attributes CTR is a 32-bit register. Figure 4-95 on page 4-189 shows the CTR bit assignments. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-188 ID021414 Non-Confidential...
Page 250 The VPIDR characteristics are: Purpose Holds the value of the Virtualization Processor ID. This is the value returned by Non-secure EL1 reads of MIDR.See MIDR bit assignments on page 4-157. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-189 ID021414 Non-Confidential...
Page 251 Provides the value of the Virtualization Multiprocessor ID. This is the value returned by Non-secure EL1 reads of MPIDR. Usage constraints This register is accessible as follows: (NS) (NS) (SCR.NS = 1) (SCR.NS = 0) ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-190 ID021414 Non-Confidential...
Page 252 Some bits in the register are read-only. These bits relate to non-configurable features of an implementation, and are provided for compatibility with previous versions of the architecture. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-191 ID021414 Non-Confidential...
Page 253 21 20 19 17 16 15 14 13 12 11 8 7 6 5 4 3 2 1 0 nTWE CP15BEN THEE nTWE UWXN Figure 4-98 SCTLR bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-192 ID021414 Non-Confidential...
Page 254 WFE wakeup event, it is taken as an exception to EL1 using the 0x1 ESR code. WFE instructions are executed as normal. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-193 ID021414 Non-Confidential...
Page 255 Instruction caches enabled. If SCTLR.M is set to 0, instruction accesses from stage 1 of the EL0/EL1 translation regime are to Normal memory, Outer Shareable, Inner Write-Through, Outer Write-Through. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-194 ID021414 Non-Confidential...
Page 256 To access the SCTLR: MRC p15, 0, <Rt>, c1, c0, 0 ; Read SCTLR into Rt MCR p15, 0, <Rt>, c1, c0, 0 ; Write Rt to SCTLR ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-195 ID021414 Non-Confidential...
Page 257: Auxiliary Control Register
ACTLR bit assignments. 7 6 5 4 3 2 L2ACTLR access control L2ECTLR access control L2CTLR access control CPUECTLR access control CPUACTLR access control Figure 4-99 ACTLR bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-196 ID021414 Non-Confidential...
Page 258 The CPACR has no effect on instructions executed at EL2. Configurations CPACR is architecturally mapped to AArch64 register CPACR_EL1. See Architectural Feature Access Control Register on page 4-57. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-197 ID021414 Non-Confidential...
Page 259 Advanced SIMD instructions, both integer and floating-point. Advanced SIMD and Floating-point registers D0-D31 and their views as S0-S31 and Q0-Q15. FPSCR, FPSID, MVFR0, MVFR1, MVFR2, FPEXC system registers. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-198 ID021414 Non-Confidential...
Page 260 SCR is a 32-bit register. Figure 4-101 shows the SCR bit assignments. 10 9 8 7 6 4 3 2 1 0 Figure 4-101 SCR bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-199 ID021414 Non-Confidential...
Page 261 Monitor mode are trapped to Monitor mode as if the instruction would otherwise cause suspension of execution. UNDEFINED [11:10] Reserved, ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-200 ID021414 Non-Confidential...
Page 262 MCR p15,0,<Rt>,c1,c1,0 ; Write Rt to SCR 4.5.31 Secure Debug Enable Register The SDER characteristics are: Purpose Controls invasive and non-invasive debug in the Secure EL0 state. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-201 ID021414 Non-Confidential...
Page 263 The NSACR characteristics are: Purpose Defines the Non-secure access permission to CP0 to CP13. Usage constraints This register is accessible as follows: (NS) (NS) (SCR.NS = 1) (SCR.NS = 0) ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-202 ID021414 Non-Confidential...
Page 264 If Advanced SIMD and Floating-point are not implemented, this bit is [9:0] Reserved, Note If the values of the cp11 and cp10 fields are not the same, the behavior is UNPREDICTABLE ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-203 ID021414 Non-Confidential...
Page 265 SDCR is a 32-bit register. Figure 4-104 shows the SDCR bit assignments. 21 20 19 17 16 15 14 13 EPMAD EDAD SPME Figure 4-104 SDCR bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-204 ID021414 Non-Confidential...
Page 266 Hyp Auxiliary Control Register The HACTLR characteristics are: Purpose Controls write access to registers in IMPLEMENTATION DEFINED Non-secure EL1 modes, such as CPUACTLR, CPUECTLR, L2CTLR, L2ECTLR and L2ACTLR. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-205 ID021414 Non-Confidential...
Page 267 Figure 4-105 shows the HACTLR bit assignments. L2ACTLR access control L2ECTLR access control L2CTLR access control CPUECTLR access control CPUACTLR access control Figure 4-105 HACTLR bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-206 ID021414 Non-Confidential...
Page 268 Provides top level control of the system operation in Hyp mode. This register provides Hyp mode control of features controlled by the Banked SCTLR bits, and shows the values of the non-Banked SCTLR bits. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-207 ID021414 Non-Confidential...
Page 269 26 25 24 22 21 20 19 18 17 16 15 14 13 12 11 3 2 1 0 1 C A CP15BEN Figure 4-106 HSCTLR bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-208 ID021414 Non-Confidential...
Page 270 When this bit is 0, all EL2 Normal memory instruction accesses are Non-cacheable. If this register is at the highest exception level implemented, field resets to 0. Otherwise, its reset value is UNKNOWN ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-209 ID021414 Non-Confidential...
Page 271 Load/store exclusive and load-acquire/store-release instructions have this alignment check regardless of the value of the A bit. If this register is at the highest exception level implemented, field resets to 0. Otherwise, its reset value is UNKNOWN ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-210 ID021414 Non-Confidential...
Page 272 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 TRVM SWIO TTLB TIDCP TID3 TID2 TID0 TID1 Figure 4-107 HCR bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-211 ID021414 Non-Confidential...
Page 274 Cache maintenance instructions by address to the point of coherency executed from EL1 or EL0 that are not to be trapped to EL2. This covers the following instructions: UNDEFINED , and DCIMVAC DCCIMVAC DCCMVAC The reset value is 0. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-213 ID021414 Non-Confidential...
Page 275 EL1 or EL0 to be trapped to EL2 if the instruction would otherwise cause suspension of execution. For example, if there is not a pending WFI wake-up event: The reset value is 0. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-214 ID021414 Non-Confidential...
Page 276 EL1 or EL0. The possible values are: No effect. 0b00 Inner Shareable. 0b01 Outer Shareable. 0b10 Full System. 0b11 The reset value is 0. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-215 ID021414 Non-Confidential...
Page 277 MCR p15, 4, <Rt>, c1, c1, 0; Write Hyp Configuration Register 4.5.37 Hyp Configuration Register 2 The HCR2 characteristics are: Purpose Provides additional configuration controls for virtualization. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-216 ID021414 Non-Confidential...
Page 278 Purpose Controls the trapping to Hyp mode of Non-secure accesses, at EL1 or lower, to functions provided by the debug and trace architectures and the Performance Monitor. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-217 ID021414 Non-Confidential...
Page 279 HDCR is a 32-bit register. Figure 4-109 shows the HDCR bit assignments. 11 10 9 8 7 6 5 4 HPMN TPMCR HPME TDOSA TDRA Figure 4-109 HDCR bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-218 ID021414 Non-Confidential...
Page 281 When this bit is set to 1, access to the performance monitors that are reserved for use from Hyp mode is enabled. For more information, see the description of the HPMN field. The reset value of this bit is UNKNOWN ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-220 ID021414 Non-Confidential...
Page 282 Trap valid Non-secure performance monitor accesses to Hyp mode. When this bit is set to 1, any valid Non-secure access to the Performance Monitor registers is trapped to Hyp mode. This bit resets to 0. See the ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture ®...
Page 283 21 20 19 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TCPAC TASE TCP10 TCP11 Figure 4-110 HCPTR bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-222 ID021414 Non-Confidential...
Page 284 If the TCP11 and TCP10 fields are set to different values, the behavior is the same as if both fields were set to the value of TCP10, in all respects other than the value read back by explicitly reading TCP11. To access the HCPTR: ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-223 ID021414 Non-Confidential...
Page 285 TTBR0 format when using the Short-descriptor translation table format Figure 4-111 shows the TTBR0 bit assignments when TTBCR.EAE is 0. TTB0 IRGN[0] IRGN[1] Figure 4-111 TTBR0 bit assignments, TTBCR.EAE is 0 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-224 ID021414 Non-Confidential...
Page 286 TTBR0 format when using the Long-descriptor translation table format Figure 4-112 shows the TTBR0 bit assignments when TTBCR.EAE is 1. ASID BADDR[47:x] Figure 4-112 TTBR0 bit assignments, TTBRC.EAE is 1 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-225 ID021414 Non-Confidential...
Page 287 This section describes: • TTBR1 format when using the Short-descriptor translation table format on page 4-227. • TTBR1 format when using the Long-descriptor translation table format on page 4-227. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-226 ID021414 Non-Confidential...
Page 288 MCR p15, 0, <Rt>, c2, c0, 1 ; Write Rt to TTBR1 TTBR1 format when using the Long-descriptor translation table format Figure 4-114 on page 4-228 shows the TTBR1 bit assignments when TTBCR.EAE is 1. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-227 ID021414 Non-Confidential...
Page 289 Configurations TTBCR (NS) is architecturally mapped to AArch64 register TCR_EL1. Translation Control Register, EL1 on page 4-86. There are separate Secure and Non-secure copies of this register. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-228 ID021414 Non-Confidential...
Page 290 When N has its reset value of 0, the translation table base is compatible with ARMv5 and ARMv6. Resets to 0. TTBCR format when using the Long-descriptor translation table format Figure 4-116 on page 4-230 shows the TTBCR bit assignments when TTBCR.EAE is 1. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-229 ID021414 Non-Confidential...
Page 291 Perform translation table walks using TTBR1. A TLB miss on an address that is translated using TTBR1 generates a Translation fault. No translation table walk is performed. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-230 ID021414 Non-Confidential...
Page 292 The size offset of the memory region addressed by TTBR0. The region size is 2 32-T0SZ bytes. Resets to 0. To access the TTBCR: MRC p15,0,<Rt>,c2,c0,0 ; Read TTBR0 into Rt MCR p15,0,<Rt>,c2,c0,0 ; Write Rt to TTBR0 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-231 ID021414 Non-Confidential...
Page 293 HTCR is a 32-bit register. Figure 4-117 shows the HTCR bit assignments. 24 23 22 14 13 12 11 10 9 T0SZ ORGN0 IRGN0 Figure 4-117 HTCR bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-232 ID021414 Non-Confidential...
Page 294 Non-secure modes other than Hyp mode, and holds cacheability and shareability information for the accesses. Usage constraints This register is accessible as follows: (NS) (NS) (SCR.NS = 1) (SCR.NS = 0) ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-233 ID021414 Non-Confidential...
Page 295 UNKNOWN [3:0] T0SZ The size offset of the memory region addressed by TTBR0. The region size is 2 32-T0SZ bytes. To access the VTCR: ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-234 ID021414 Non-Confidential...
Page 296 To access the DACR: MRC p15, 0, <Rt>, c3, c0, 0 ; Read DACR into Rt MCR p15, 0, <Rt>, c3, c0, 0 ; Write Rt to DACR ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-235 ID021414 Non-Confidential...
Page 297 This register is accessible only at EL2 or EL3. Attributes HSTR is a 32-bit register. Figure 4-120 shows the HSTR bit assignments. TTEE Figure 4-120 HSTR bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-236 ID021414 Non-Confidential...
Page 298 Has no effect on Non-secure accesses to CP15 registers. Trap valid Non-secure accesses to coprocessor primary register CRn = 10 to Hyp mode. The reset value is 0. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-237 ID021414 Non-Confidential...
Page 299 To access the HSTR: MRC p15, 4, <Rt>, c1, c1, 3 ; Read HSTR into Rt MCR p15, 4, <Rt>, c1, c1, 3 ; Write Rt to HSTR ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-238 ID021414 Non-Confidential...
Page 300 DFSR bit assignments when using the Short-descriptor translation table format. 14 13 12 11 10 9 8 7 Domain FS[3:0] FS[4] Figure 4-121 DFSR bit assignments for Short-descriptor translation table format ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-239 ID021414 Non-Confidential...
Page 301 Synchronous parity error on memory access. 0b11001 Synchronous parity error on translation table walk, first level. 0b11100 Synchronous parity error on translation table walk, second level. 0b11110 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-240 ID021414 Non-Confidential...
Page 302 DFSR bit assignments when using the Long-descriptor translation table format. 14 13 12 11 10 9 8 Status Figure 4-122 DFSR bit assignments for Long-descriptor translation table format ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-241 ID021414 Non-Confidential...
Page 303 Synchronous parity error on memory access on translation table walk, first level, LL bits indicate 0b0111LL level. Alignment fault. 0b100001 Debug event. 0b100010 TLB conflict abort. 0b110000 abort. 0b110101 LDREX STREX ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-242 ID021414 Non-Confidential...
Page 304 IFSR bit assignments when using the Short-descriptor translation table format. 13 12 11 10 9 8 FS[3:0] FS[4] Figure 4-123 IFSR bit assignments for Short-descriptor translation table format ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-243 ID021414 Non-Confidential...
Page 305 IFSR bit assignments when using the Long-descriptor translation table format. 13 12 11 10 9 8 Status Figure 4-124 IFSR bit assignments for Long-descriptor translation table format ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-244 ID021414 Non-Confidential...
Page 306 UNKNOWN To access the IFSR: MRC p15, 0, <Rt>, c5, c0, 1; Read IFSR into Rt MCR p15, 0, <Rt>, c5, c0, 1; Write Rt to IFSR ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-245 ID021414 Non-Confidential...
Page 307 This register is accessible only at EL2 or EL3. Attributes HSR is a 32-bit register. Figure 4-125 shows the HSR bit assignments. 26 25 24 Figure 4-125 HSR bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-246 ID021414 Non-Confidential...
Page 308 Table 4-223 HSR bit assignments Bits Name Function [31:26] Exception class. The exception class for the exception that is taken in Hyp mode. See the ARM Architecture ® Reference Manual ARMv8, for ARMv8-A architecture profile for more information. [25] Instruction length. See the ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for ®...
Page 309 Attributes IFAR is a 32-bit register. Figure 4-127 shows the IFAR bit assignments. VA of faulting address of synchronous Prefetch Abort exception Figure 4-127 IFAR bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-248 ID021414 Non-Confidential...
Page 310 To access the HDFAR: MRC p15, 4, <Rt>, c6, c0, 0 ; Read HDFAR into Rt MCR p15, 4, <Rt>, c6, c0, 0 ; Write Rt to HDFAR ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-249 ID021414 Non-Confidential...
Page 311 4.5.59 Hyp IPA Fault Address Register The HPFAR characteristics are: Purpose Holds the faulting IPA for some aborts on a stage 2 translation taken to Hyp mode. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-250 ID021414 Non-Confidential...
Page 312 Architecture Reference Manual ARMv8, for ® ARMv8-A architecture profile for more information. 4.5.61 L2 Control Register The L2CTLR characteristics are: Purpose Provides control options for the L2 memory IMPLEMENTATION DEFINED system. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-251 ID021414 Non-Confidential...
Page 313 Number of cores L2 Data RAM input latency Reserved SCU- L2 cache protection Reserved CPU Cache Protection L2 Data RAM output latency Figure 4-131 L2CTLR bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-252 ID021414 Non-Confidential...
Page 314 The L2ECTLR characteristics are: Purpose Provides additional control options for the L2 IMPLEMENTATION DEFINED memory system. This register is used for dynamically changing, but implementation specific, control bits. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-253 ID021414 Non-Confidential...
Page 315 Figure 4-132 shows the L2ECTLR bit assignments. AXI or AMBA 5 CHI asynchronous error L2 dynamic retention control L2 internal asynchronous error Figure 4-132 L2ECTLR bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-254 ID021414 Non-Confidential...
Page 316 0b111 To access the L2ECTLR: MRC p15, 1, <Rt>, c9, c0, 3; Read L2ECTLR into Rt MCR p15, 1, <Rt>, c9, c0, 3; Write Rt to L2ECTLR ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-255 ID021414 Non-Confidential...
Page 317 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TR7 TR6 TR5 TR4 TR3 TR2 TR1 TR0 NOS7 NOS0 NOS6 NOS1 NOS5 NOS2 NOS4 NOS3 Figure 4-133 PRRR bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-256 ID021414 Non-Confidential...
Page 318 4-258. This field defines the mapped memory type for a region with attributes n. The possible values of the field are: Device (nGnRnE). 0b00 Device (not nGnRnE). 0b01 Normal Memory. 0b10 Reserved, effect is UNPREDICTABLE 0b11 a. Where n is 0-7. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-257 ID021414 Non-Confidential...
Page 319 To access the PRRR: MRC p15, 0, <Rt>, c10, c2, 0 ; Read PRRR into Rt MCR p15, 0, <Rt>, c10, c2, 0 ; Write Rt to PRRR ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-258 ID021414 Non-Confidential...
Page 320 MAIR0 and MAIR1 bit assignments. 24 23 16 15 MAIR0 Attr3 Attr2 Attr1 Attr0 MAIR1 Attr7 Attr6 Attr5 Attr4 Figure 4-134 MAIR0 and MAIR1 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-259 ID021414 Non-Confidential...
Page 321 , RW not Normal Memory, Inner Write-through non-transient UNPREDICTABLE 0b10RW Device-GRE memory Normal Memory, Inner Write-back non-transient (RW=00) 0b1100 , RW not Normal Memory, Inner Write-back non-transient UNPREDICTABLE 0b11RW ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-260 ID021414 Non-Confidential...
Page 322 To access the MAIR1: MRC p15, 0, <Rt>, c10, c2, 1 ; Read MAIR1 into Rt MCR p15, 0, <Rt>, c10, c2, 1 ; Write Rt to MAIR1 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-261 ID021414 Non-Confidential...
Page 323 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OR7 OR6 OR5 OR4 OR3 OR2 Figure 4-135 NMRR bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-262 ID021414 Non-Confidential...
Page 324 Monitor mode or to Hyp mode when high exception vectors are not selected. Usage constraints This register is accessible as follows: (NS) (NS) (SCR.NS = 1) (SCR.NS = 0) ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-263 ID021414 Non-Confidential...
Page 325 There is one copy of this register that is used in both Secure and Non-secure states. Attributes RMR is a 32-bit register. Figure 4-136 shows the RMR bit assignments. AA64 Figure 4-136 RMR bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-264 ID021414 Non-Confidential...
Page 326 There is one copy of this register that is used in both Secure and Non-secure states. Attributes ISR is a 32-bit register. Figure 4-137 on page 4-266 shows the ISR bit assignments. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-265 ID021414 Non-Confidential...
Page 327 (NS) (SCR.NS = 1) (SCR.NS = 0) Configurations The HVBAR is: • Architecturally mapped to the AArch64 VBAR_EL2[31:0]. See Vector Base Address Register, EL2 on page 4-120. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-266 ID021414 Non-Confidential...
Page 328 You can write to this register only when the L2 memory system is idle. ARM recommends that you write to this register after a powerup reset before the MMU is enabled and before any ACE, CHI or ACP traffic has begun.
Page 329 Reserved, To access the L2ACTLR: MRC p15, 1, <Rt>, c15, c0, 0; Read L2ACTLR into Rt MCR p15, 1, <Rt>, c15, c0, 0; Write Rt to L2ACTLR ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-268 ID021414 Non-Confidential...
Page 330 (SCR.NS = 0) The CPU Auxiliary Control Register can be written only when the system is idle. ARM recommends that you write to this register after a powerup reset, before the MMU is enabled, and before any ACE or ACP traffic begins.
Page 331 Disable ReadUnique request for prefetch streams initiated by STB accesses: ReadUnique used for prefetch streams initiated from STB accesses. This is the reset value. ReadShared used for prefetch streams initiated from STB accesses. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-270 ID021414 Non-Confidential...
Page 332 MCRR p15, 0, <Rt>, <Rt2>, c15; Write CPU Auxiliary Control Register 4.5.77 CPU Extended Control Register The CPUECTLR characteristics are: Purpose Provides additional configuration and control IMPLEMENTATION DEFINED options for the processor. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-271 ID021414 Non-Confidential...
Page 333 CPUECTLR is a 64-bit register. Figure 4-141 shows the CPUECTLR bit assignments. 7 6 5 SMPEN Advanced-SIMD/FP retention control CPU retention control Figure 4-141 CPUECTLR bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-272 ID021414 Non-Confidential...
Page 334 Holds ECC errors on the: • L1 data RAMs. • L1 tag RAMs. • TLB RAMs. This register is used for recording ECC errors on all processor RAMs. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-273 ID021414 Non-Confidential...
Page 335 40 39 24 23 21 20 18 17 12 11 Other error Repeat error RAMID RAM address count count Fatal Valid CPUID/Way Figure 4-142 CPUMERRSR bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-274 ID021414 Non-Confidential...
Page 336 Indicates the index address of the first memory error. Note • A fatal error results in the RAMID, Way, and RAM address recording the fatal error, even if the sticky bit is set. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-275 ID021414 Non-Confidential...
Page 337 L2MERRSR bit assignments. 40 39 24 23 22 21 18 17 Other error Repeat error RAMID RAM address count count Fatal Valid CPUID/Way Figure 4-143 L2MERRSR bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-276 ID021414 Non-Confidential...
Page 338 If two or more first memory error events from different RAMs occur in the same cycle, one of the errors is selected arbitrarily, while the Other error count field is incremented only by one. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-277 ID021414 Non-Confidential...
Page 339 The input PERIPHBASE[31:18] determines the reset value. [17:8] Reserved, [7:0] PERIPHBASE[39:32] The input PERIPHBASE[39:32] determines the reset value. To access the CBAR: MRC p15, 1, <Rt>, c15, c3, 0; Read CBAR into Rt ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-278 ID021414 Non-Confidential...
Page 340 This chapter describes the Memory Management Unit (MMU). It contains the following sections: • About the MMU on page 5-2. • TLB organization on page 5-3. • TLB match process on page 5-4. • External aborts on page 5-5. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 341: Chapter 5 Memory Management Unit
AArch64 state, the ARMv8 address translation system resembles an extension to the Long Descriptor Format address translation system to support the expanded virtual and physical address spaces. For more information regarding the address translation formats, see the ARM ® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile. Key differences...
Page 342: Tlb Organization
If the stage 1 translation results in a section or larger mapping then nothing is placed in the walk cache. The walk cache holds entries fetched from Secure and Non-secure state. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 343: Tlb Match Process
For a request originating from EL2 or AArch64 EL3, the ASID and VMID match are ignored. • For a request not originating from Non-secure EL0 or EL1, the VMID match is ignored. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 344: External Aborts
Externally generated aborts during a data read or write can be asynchronous. For a load multiple or store multiple operation, the address captured in the fault address register is that of the address that generated the synchronous external abort. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 345 L1 Instruction memory system on page 6-7. • L1 Data memory system on page 6-9. • Data prefetching on page 6-12. • Direct access to internal memory on page 6-13. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 346: Chapter 6 Level 1 Memory System
Support for three outstanding data cache misses. • Merging store buffer capability. This handles writes to: — Device memory. — Normal Cacheable memory. — Normal Non-cacheable memory. • Data side prefetch engine. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 347: Cache Behavior
XN (Execute Never) attribute bit. To avoid speculative fetches to read-sensitive devices when address translation is disabled, these devices and code that are fetched must be separated in the physical memory map. See the ARM Architecture Reference ®...
Page 348 A secondary read allocate mode applies when the L2 cache is integrated. After a threshold number of consecutive cache line sized writes to L2 are detected, L2 read allocate mode is entered. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 349 The Cortex-A53 processor automatically invalidates caches on reset unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins. It is therefore not necessary for software to invalidate the caches on startup. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 350: Support For V8 Memory Types
ARMv8 Device memory, they do not apply to Normal memory. If an ARMv7 architecture operating system runs on a Cortex-A53 processor, the Device memory type matches the nGnRE encoding and the Strongly-Ordered memory type matches the nGnRnE memory type. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 351: L1 Instruction Memory System
• (immediate) in AArch32 state. • (register) in AArch32 state. • in AArch64 state. In AArch32 state, the following instructions cause a return stack pop if predicted: • ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 352 Because return-from-exception instructions can change processor privilege mode and security state, they are not predicted. This includes: • LDM (exception return) • • SUBS pc, lr • ERET ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 353: L1 Data Memory System
However, if the address being accessed by the exclusive code sequence is in cacheable memory, any eviction of the cache line containing that address clears the monitor. ARM therefore recommends that no load or store instructions are placed between the exclusive load and the exclusive store because these additional instructions can cause a cache eviction.
Page 354 See the ARM AMBA AXI and ACE Protocol Specification AXI3, AXI4, and AXI4-Lite, ACE ® ® and ACE-Lite for more information about ACE transactions. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 6-10 ID021414 Non-Confidential...
Page 355 WriteUniqueFull WriteUniquePtl if not allocating into the cache. See the ARM AMBA 5 CHI Protocol Specification for more information about CHI ® ® transactions. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 6-11 ID021414 Non-Confidential...
Page 356: Data Prefetching
This enables a block of 64 bytes in memory, aligned to 64 bytes in size, to be set to zero. If the instruction misses in the cache, it clears main memory, without causing an L1 DC ZVA or L2 cache allocation. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 6-12 ID021414 Non-Confidential...
Page 357: Direct Access To Internal Memory
Instruction Cache Data Read Operation Register Write-only Set/Way/Offset MCR p15, 3, <Rd>, c15, c4, 1 TLB Data Read Operation Register Write-only Index/Way MCR p15, 3, <Rd>, c15, c4, 2 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 6-13 ID021414 Non-Confidential...
Page 358 Tag Address [11]. Data Register 0 [30:6] Reserved, Data Register 0 Parity bit if ECC is implemented, otherwise Data Register 0 Dirty copy bit if ECC is implemented, otherwise ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 6-14 ID021414 Non-Confidential...
Page 359 (Instruction cache size (Byte) / 2*32)) for the 2-way set-associative cache. Table 6-9 Instruction cache tag and data location encoding Bit-field of Rd Description [31] Cache Way [30:S+5] Unused [S+4:6] Set index [5:2] Line offset [1:0] Unused ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 6-15 ID021414 Non-Confidential...
Page 360 TLB Data Read Operation Register location encoding of Rd. Table 6-11 TLB Data Read Operation Register location encoding Bits Description [31:30] TLB way [29:8] Unused [7:0] TLB index ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 6-16 ID021414 Non-Confidential...
Page 361 Memory Type and shareability Table 6-14 on page 6-18. [96] Stage2 executable permissions. [95] XS1Nonusr Non user mode executable permissions. [94] XS1Usr User mode executable permissions. [93:66] Physical Address. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 6-17 ID021414 Non-Confidential...
Page 362 Table 6-14 Main TLB memory types and shareability Bits Memory type Description Device Non-coherent, Outer WB Non-coherent, Outer NC Non-coherent, Outer WT Coherent, Inner WB and Outer WB ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 6-18 ID021414 Non-Confidential...
Page 363 Device type: nGnRnE. nGnRE. nGRE. GRE. Non-coherent, Outer WB Outer allocation hint: Non-coherent, Outer WT Coherent, Inner WB and Outer WB WRA. Non-coherent, Outer NC Inner type: Unused. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 6-19 ID021414 Non-Confidential...
Page 364 Set if the entry was fetched in EL2 mode. [8:1] Attrs Physical attributes of the final level stage 1 table. Valid Valid bit: Entry does not contain valid data. Entry contains valid data. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 6-20 ID021414 Non-Confidential...
Page 365 Contiguous Set if the pagewalk had contiguous bit set. [9:6] Memattrs Memory attributes. Execute Never. [4:3] Hypervisor access permissions. [2:1] Shareability. Valid The entry contains valid data. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 6-21 ID021414 Non-Confidential...
Page 366 7-6. • CHI master interface on page 7-13. • Additional memory attributes on page 7-17. • Optional integrated L2 cache on page 7-18. • ACP on page 7-19. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 367: Chapter 7 Level 2 Memory System
Optional ACP interface if an L2 cache is configured. — Optional ECC protection. The L2 memory system has a synchronous abort mechanism and an asynchronous abort mechanism, see External aborts handling on page 7-18. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 368: Snoop Control Unit
BROADCASTCACHEMAINT BROADCASTOUTER BROADCASTINNER a. SYSBARDISABLE must be set to HIGH in AXI3 mode. b. ACE non-coherent is compatible with connecting to an ACE-Lite interconnect. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 369 L3 cache with L3 cache Cache maintenance requests on TXREQ channel Snoops on RXREQ channel Coherent requests on TXREQ channel DVM requests on TXREQ channel ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 370 L1 or L2 cache, but the line in the cache is in a shareability domain that does not extend beyond the cluster, then the snoop is treated as missing in the cluster. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 371: Ace Master Interface
Only Device memory types with nGnRnE or nGnRE can have more than one outstanding transaction with the same AXI ID. All other memory types use a unique AXI ID for every outstanding transaction. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 372 Core nn non-re-orderable device write 0b011nn Write to normal memory, or re-orderable device memory 0b1xxxx a. Where nn is the core number , or 0b00 0b01 0b10 0b11 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 373 0b10 0b11 Note These ID and transaction details are provided for information only. ARM strongly recommends that all interconnects and peripherals are designed to support any type and number of transactions on any ID, to ensure compatibility with future products.
Page 374 DMB and DSB instructions. DVM sync snoops received from the interconnect. WriteNoSnoop Non-cacheable store instructions. Evictions of non-shareable cache lines from L1 and L2. WriteUnique Not used. WriteLineUnique Not used. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 375 — ReadClean. See the ARM AMBA AXI and ACE Protocol Specification AXI3, AXI4, and AXI4-Lite, ACE ® ® and ACE-Lite for more information about the ACE channel. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 7-10 ID021414 Non-Confidential...
Page 376 This means that the write must be observable to all other masters in the system. ARM expects the majority of peripherals to meet this requirement. For best performance, ARM recommends that barriers are terminated within the cluster.
Page 377 Cortex-A53 processor marks the transaction as privileged, even it if was initiated by an unprivileged process. Table 7-10 shows Cortex-A53 processor exception levels and corresponding ARPROTM[0] and AWPROTM[0] values. Table 7-10 Cortex-A53 MPCore mode and ARPROT and AWPROT values Value of ARPROT[0] Processor exception level Type of access and AWPROT[0]...
Page 378: Chi Master Interface
Unlike an AMBA 4 ACE configured Cortex-A53 processor, there is never any ID reuse, regardless of the memory type. a. n is the number of cores. m is the ACP interface. w is the write issuing capability plus one. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 7-13 ID021414 Non-Confidential...
Page 379 Evictions of dirty lines from the L2 cache, when the line is still present in an L1 cache. Some cache maintenance instructions. WriteCleanPtl Not used. WriteEvictFull Evictions of unique clean lines, when configured in the L2ACTLR. Evict Evictions of clean lines, when configured in the L2ACTLR. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 7-14 ID021414 Non-Confidential...
Page 380 Can be produced on the CHI master interface except: — ReadClean. — WriteBackPtl. — WriteCleanPtl. See the ARM AMBA 5 CHI Protocol Specification for more information about the CHI ® ® channel. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 7-15 ID021414 Non-Confidential...
Page 381 Addresses that map to an HN-F node can be marked as cacheable memory in the page tables, and can take part in the cache coherency protocol. Addresses that map to an HN-I or MN must be marked as device or non-cacheable memory. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 7-16 ID021414 Non-Confidential...
Page 382: Additional Memory Attributes
10RW 11RW Where is read allocate hint, is write allocate hint. Inner shareable. Anything with bit[7] set must also have bit[2] set. [1:0] Inner memory type: Device. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 7-17 ID021414 Non-Confidential...
Page 383: Optional Integrated L2 Cache
When nEXTERRIRQ is asserted it remains asserted until the error is cleared by a write of 0 to the AXI or CHI asynchronous error bit of the L2ECTLR register. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 7-18 ID021414...
Page 384: Acp
— AWADDR aligned to 16 byte boundary, so AWADDR[3:0] is — AWSIZE and AWBURST assume values of and INCR respectively. 0b100 — WSTRB can take any value. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 7-19 ID021414 Non-Confidential...
Page 385 The master must avoid sending more than one outstanding transaction on the same AXI ID, to prevent the second transaction stalling the interface until the first has completed. If the master requires explicit ordering between two transactions, ARM recommends that it waits for the response to the first transaction before sending the second transaction.
Page 386: Chapter 8 Cache Protection
Cache Protection This chapter describes the Cortex-A53 CPU cache protection. It contains the following sections: • Cache protection behavior on page 8-2. • Error reporting on page 8-4. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 387: Cache Protection Behavior
ECC, CPU_CACHE_PROTECTION 32 bits Line cleaned and invalidated from L1, with SECDED single bit errors corrected as part of the eviction. Line refetched from L2 or external memory. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 388 The page tables have been modified since the first execution, resulting in an instruction or data abort trap being taken on re-execution. The register file is updated with data that was successfully read, before the correctable ECC error occurred. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 389: Error Reporting
0 to the L2 internal asynchronous error bit of the L2ECTLR register. • ARM recommends that the nINTERRIRQ pin is connected to the interrupt controller so that an interrupt or system error is generated when the pin is asserted.
Page 390 Chapter 9 Generic Interrupt Controller CPU Interface This chapter describes the Cortex-A53 processor implementation of the ARM Generic Interrupt Controller (GIC) CPU interface. It contains the following sections: • About the GIC CPU Interface on page 9-2. • GIC programmers model on page 9-3.
Page 391: Chapter 9 Generic Interrupt Controller Cpu Interface
GICv3 or GICv4 distributor component in the system, by asserting the GICCDISABLE signal HIGH at reset. Asserting the GICCDISABLE signal HIGH at reset removes access to the memory-mapped and system GIC CPU Interface registers. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 392: Gic Programmers Model
• Determining the highest priority pending interrupt for the processor. • Generating SGIs. For more information on the CPU interface, see the ARM Generic Interrupt Controller Architecture Specification. Table 9-2 on page 9-4 lists the registers for the CPU interface.
Page 393 S = Secure. b. NS = Non-secure. 9.2.3 CPU interface register descriptions This section describes only registers whose implementation is specific to the Cortex-A53 processor. All other registers are described in the ARM Generic Interrupt Controller ® Architecture Specification Table 9-2 provides cross-references to individual registers.
Page 394 Identifies the revision number for the CPU interface: r0p2. [11:0] Implementer Contains the JEP106 code of the company that implements the CPU interface. For an ARM implementation, these values are: Bits[11:8] = The JEP106 continuation code of the implementer. Bit[7] Always 0.
Page 395 List Register 3 0x00000000 9.2.5 Virtual interface control register descriptions This section describes only registers whose implementation is specific to the Cortex-A53 processor. All other registers are described in the ARM Generic Interrupt Controller ® Architecture Specification. Table 9-5 provides cross-references to individual registers.
Page 396 VM Aliased Highest Priority Pending Interrupt Register 0x000003FF GICV_APR0 VM Active Priority Register on page 9-8 0x00000000 GICV_IIDR VM CPU Interface Identification Register on page 9-8 0x0034143B GICV_DIR VM Deactivate Interrupt Register ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 397 Generic Interrupt Controller CPU Interface 9.2.7 Virtual CPU interface register descriptions This section describes only registers whose implementation is specific to the Cortex-A53 processor. All other registers are described in the ARM Generic Interrupt Controller ® Architecture Specification. Table 9-7 on page 9-7 provides cross-references to individual registers.
Page 398 Chapter 10 Generic Timer This chapter describes the Cortex-A53 processor implementation of the ARM Generic Timer. It contains the following sections: • About the Generic Timer on page 10-2. • Generic Timer functional description on page 10-3. • Generic Timer register summary on page 10-4.
Page 399: Chapter 10 Generic Timer
The Cortex-A53 MPCore Generic Timer is compliant with the ARM Architecture Reference ® Manual ARMv8, for ARMv8-A architecture profile. This chapter describes only features that are specific to the Cortex-A53 MPCore implementation. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved.
Page 400: Generic Timer Functional Description
EL1 Secure physical timer event nCNTHPIRQ[n:0] EL2 physical timer event nCNTVIRQ[n:0] Virtual timer event a. n is the number of cores present in the cluster, minus one. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 10-3 ID021414 Non-Confidential...
Page 401: Generic Timer Register Summary
32-bits wide or 64-bits wide and accessible in the AArch32 and AArch64 Execution states. 10.3.1 AArch64 Generic Timer register summary Table 10-2 shows the AArch64 Generic Timer registers. See the ARM Architecture Reference ® Manual ARMv8, for ARMv8-A architecture profile for information about these registers. Table 10-2 AArch64 Generic Timer registers...
Page 402 The reset value for bit[2] is 0 and for bits[1:0] is 10.3.2 AArch32 Generic Timer register summary Table 10-3 shows the AArch32 Generic Timer registers. See the ARM Architecture Reference ® Manual ARMv8, for ARMv8-A architecture profile for information about these registers.
Page 403 11-21. • Memory-mapped register descriptions on page 11-25. • Debug events on page 11-36. • External debug interface on page 11-37. • ROM table on page 11-41. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-1 ID021414 Non-Confidential...
Page 404: Chapter 11 Debug
This section gives an overview of debug and describes the debug components. The processor forms one component of a debug system. The following methods of debugging an ARM processor based SoC exist: Conventional JTAG debug (‘external’ debug) This is invasive debug with the core halted using: •...
Page 405 • Application software. • Operating systems. • Hardware systems based on an ARM processor. The debug unit enables you to: • Stop program execution. • Examine and alter process and coprocessor state.
Page 406: Debug Register Interfaces
This signal resets some of the debug and performance monitor logic. This maps to a warm reset that covers reset of the processor logic. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-4 ID021414 Non-Confidential...
Page 407 Stop at the first column a condition is true, the entry gives the access permission of the register and scanning stops. Table 11-2 External register condition code example OSLK EDAD Default RO/WI ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-5 ID021414 Non-Confidential...
Page 408: Aarch64 Debug Register Summary
The 64-bit registers cover two addresses on the external memory interface. For those registers not described in this chapter, see the ARM Architecture Reference Manual ARMv8, for ARMv8-A ®...
Page 409 Debug Claim Tag Set Register 0x000000FF DBGCLAIMCLR_EL1 Debug Claim Tag Clear Register 0x00000000 DBGAUTHSTATUS_EL1 Debug Authentication Status Register a. Resets to the physical address of the ROM table +3. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-7 ID021414 Non-Confidential...
Page 410: Aarch64 Debug Register Descriptions
UNKNOWN Figure 11-2 shows the DBGBCRn_EL1 bit assignments. 24 23 20 19 16 15 5 4 3 2 1 0 PMC E Figure 11-2 DBGBCRn_EL1 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-8 ID021414 Non-Confidential...
Page 411 This bit must be interpreted with the SSC and PMC fields to determine the mode and security states that can be tested. See the ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for possible values of ® the fields. [12:9] Reserved, ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-9 ID021414 Non-Confidential...
Page 412 MCR p14, 0, <Rt>, c0, cn, 4; Write Debug Breakpoint Control Register n The DBGBCRn_EL1 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0x4n8 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-10 ID021414 Non-Confidential...
Page 413 1 and 2 are reserved. See the ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for the meanings of ® watchpoint address range mask values. [23:21] Reserved, ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-11 ID021414 Non-Confidential...
Page 414 Unlinked data address match. Linked data address match. When this bit is set to 1 the linked BRP number field indicates the BRP that this WRP is linked. See the ARM ® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for more information.
Page 415 The DBGCLAIMSET_EL1characteristics are: Purpose Used by software to set CLAIM bits to 1. Usage constraints This register is accessible as follows: (NS) (SCR.NS = 1) (SCR.NS = 0) ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-13 ID021414 Non-Confidential...
Page 416 MRS <Xt>, DBGCLAIMSET_EL1 ; Read DBGCLAIMSET_EL1 into Xt MSR DBGCLAIMSET_EL1, <Xt> ; Write Xt to DBGCLAIMSET_EL1 The DBGCLAIMSET_EL1 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFA0 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-14 ID021414 Non-Confidential...
Page 417: Aarch32 Debug Register Summary
CRn, op2, CRm, Op1 or instructions in the MCRR MRRC order of CRm, Op1. For those registers not described in this chapter, see the ARM Architecture ® Reference Manual ARMv8, for ARMv8-A architecture profile. See the...
Page 418 Previously defined the offset from the base address defined in DBGDRAR of the physical base address of the debug registers for the processor. This register is now deprecated and ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-16 ID021414...
Page 419: Aarch32 Debug Register Descriptions
The number of BRPs that can be used for Context matching. This is one more than the value of this field. The value is: The processor implements two Context matching breakpoints, breakpoints 4 and 5. This field has the same value as ID_AA64DFR0_EL1.CTX_CMPs. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-17 ID021414 Non-Confidential...
Page 420 DBGDEVID bit assignments. 28 27 24 23 20 19 16 15 12 11 CIDMask AuxRegs DoubleLock VirtExtns PCsample WPAddrMask BPAddrMask VectorCatch Figure 11-6 DBGDEVID bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-18 ID021414 Non-Confidential...
Page 421 There is one copy of this register that is used in both Secure and Non-secure states. Attributes See the register summary in Table 11-7 on page 11-15. Figure 11-7 on page 11-20 shows the DBGDEVID1 bit assignments. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-19 ID021414 Non-Confidential...
Page 422 To access the DBGDEVID1 in AArch32 Execution state, read the CP14 register with: MRC p14, 0, <Rt>, c7, c1, 47 Read Debug Device ID Register 1 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-20 ID021414 Non-Confidential...
Page 423: Memory-Mapped Register Summary
External Debug Processor Status Register 0x314 Reserved 0x318-0x3FC DBGBVR0_EL1[31:0] Debug Breakpoint Value Register 0 0x400 DBGBVR0_EL1[63:32] 0x404 DBGBCR0_EL1 Debug Breakpoint Control Registers, EL1 on page 11-8 0x408 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-21 ID021414 Non-Confidential...
Page 424 Debug Watchpoint Control Registers, EL1 on page 11-11 0x818 Reserved 0x81C DBGWVR2_EL1[31:0] Debug Watchpoint Value Register 2 0x820 DBGWVR2_EL1[63:32] 0x824 DBGWCR2_EL1 Debug Watchpoint Control Registers, EL1 on page 11-11 0x828 Reserved 0x82C ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-22 ID021414 Non-Confidential...
Page 425 External Debug Device Affinity Register 1, 0xFAC EDLAR External Debug Lock Access Register 0xFB0 EDLSR External Debug Lock Status Register 0xFB4 DBGAUTHSTATUS_EL1 Debug Authentication Status Register 0xFB8 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-23 ID021414 Non-Confidential...
Page 426 EDCIDR1 Component Identification Register 1 on page 11-33 0xFF4 EDCIDR2 Component Identification Register 2 on page 11-33 0xFF8 EDCIDR3 Component Identification Register 3 on page 11-34 0xFFC ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-24 ID021414 Non-Confidential...
Page 427: Memory-Mapped Register Descriptions
0xF00 11.8.2 External Debug Device ID Register 0 The EDDEVID characteristics are: Purpose Provides extra information for external debuggers about features of the debug implementation. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-25 ID021414 Non-Confidential...
Page 428 The EDDEVID1 is in the Debug power domain. Attributes See the register summary in Table 11-11 on page 11-21. Figure 11-10 on page 11-27 shows the EDDEVID1 bit assignments. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-26 ID021414 Non-Confidential...
Page 429 0xFC4 11.8.4 Peripheral Identification Registers The Peripheral Identification Registers provide standard information required for all components that conform to the ARM Debug Interface v5 specification. They are a set of eight registers, listed in register number order in Table 11-15.
Page 430 The EDPIDR1 is in the Debug power domain. Attributes See the register summary in Table 11-11 on page 11-21. Figure 11-12 on page 11-29 shows the EDPIDR1 bit assignments. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-28 ID021414 Non-Confidential...
Page 431 Function [31:8] Reserved, [7:4] DES_0 ARM Limited. This is the least significant nibble of JEP106 ID code. [3:0] Part_1 Most significant nibble of the debug part number. The EDPIDR1 can be accessed through the internal memory-mapped interface and the external...
Page 432 JEDEC RAO. Indicates a JEP106 identity code is used. [2:0] DES_1 ARM Limited. This is the most significant nibble of JEP106 ID code. 0b011 The EDPIDR2 can be accessed through the internal memory-mapped interface and the external debug interface, offset...
Page 433 Size of the component. Log2 the number of 4KB pages from the start of the component to the end of the component ID registers. [3:0] DES_2 ARM Limited. This is the least significant nibble JEP106 continuation code. The EDPIDR4 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFD0 Peripheral Identification Register 5-7 No information is held in the Peripheral ID5, Peripheral ID6 and Peripheral ID7 Registers.
Page 434 0xFF4 Component ID2 0x05 0xFF8 Component ID3 0xB1 0xFFC The Component Identification Registers identify Debug as an ARM Debug Interface v5 component. The Component ID registers are: • Component Identification Register • Component Identification Register 1 on page 11-33. •...
Page 435 The EDCIDR1 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFF4 Component Identification Register 2 The EDCIDR2 characteristics are: Purpose Provides information to identify an external debug component. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-33 ID021414 Non-Confidential...
Page 436 The EDCIDR3 is in the Debug power domain. Attributes See the register summary in Table 11-11 on page 11-21. Figure 11-19 on page 11-35 shows the EDCIDR3 bit assignments. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-34 ID021414 Non-Confidential...
Page 437 Name Function [31:8] Reserved, [7:0] PRMBL_3 Preamble byte 3. 0xB1 The EDCIDR3 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFFC ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-35 ID021414 Non-Confidential...
Page 438: Debug Events
Debug OS Lock must be cleared. For more information, see the ARM Architecture Reference Manual ARMv8, for ARMv8-A ® architecture profile. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-36 ID021414 Non-Confidential...
Page 439: 11.10 External Debug Interface
The system can access memory-mapped debug registers through the APB interface. The APB interface is compliant with the AMBA 4 APB interface. Figure 11-20 shows the debug interface implemented in the Cortex-A53 processor. For more information on these signals, see the ARM CoreSight Architecture Specification. ®...
Page 440 0x01000 0x10FFF CPU 0 PMU 0x11000 0x11FFF CPU 1 Debug 0x12000 0x12FFF CPU 1 PMU 0x13000 0x13FFF CPU 2 Debug 0x14000 0x14FFF CPU 2 PMU 0x15000 0x15FFF ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-38 ID021414 Non-Confidential...
Page 441 The DBGL1RSTDISABLE signal applies to all cores in the cluster. Each core samples the signal when nCORERESET or nCPUPORESET is asserted. If the functionality offered by the DBGL1RSTDISABLE input signal is not required, the input must be tied to LOW. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-39 ID021414 Non-Confidential...
Page 442 Instruction Transfer Register, EDITR, while in debug state. The relevant combinations of the DBGEN, NIDEN, SPIDEN, and SPNIDEN values can be determined by polling DBGAUTHSTATUS_EL1. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-40 ID021414 Non-Confidential...
Page 443: 11.11 Rom Table
Debug 11.11 ROM table The Cortex-A53 processor includes a ROM table that complies with the ARM CoreSight ® ™ Architecture Specification. This table contains a list of components such as processor debug units, processor Cross Trigger Interfaces (CTIs), processor Performance Monitoring Units (PMUs) and processor Embedded Trace Macrocell (ETM) trace units.
Page 444 See the register summary in Table 11-28 on page 11-41. Figure 11-21 shows the bit assignments for a ROMENTRY register. Address offset Format Component present Figure 11-21 ROMENTRY bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-42 ID021414 Non-Confidential...
Page 445 0x00140003 ROMENTRY8 Core 2 Debug 0x00210 0x00210003 ROMENTRY9 Core 2 CTI 0x00220 0x00220003 ROMENTRY10 Core 2 PMU 0x00230 0x00230003 ROMENTRY11 Core 2 ETM trace unit 0x00240 0x00240003 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-43 ID021414 Non-Confidential...
Page 446 0x00016003 ROMENTRY13 Core 3 CTI 0x0001B 0x0001B003 ROMENTRY14 Core 3 PMU 0x00017 0x00017003 ROMENTRY15 Core 3 ETM trace unit 0x0001F 0x0001F003 a. If the component is present. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-44 ID021414 Non-Confidential...
Page 447 Debug 11.11.4 Peripheral Identification Registers The Peripheral Identification Registers provide standard information required for all components that conform to the ARM Debug Interface v5 specification. There is a set of eight registers, listed in register number order in Table 11-32.
Page 448 Bits Name Function [31:8] Reserved, [7:4] DES_0 Least significant nibble of JEP106 ID code. For ARM Limited. [3:0] Part_1 Most significant nibble of the ROM table part number. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-46 ID021414...
Page 449 JEDEC RAO. Indicates a JEP106 identity code is used. [2:0] DES_1 Designer, most significant bits of JEP106 ID code. For ARM Limited. 0b011 The ROMPIDR2 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFE8...
Page 450 The ROMPIDR4 is in the Debug power domain. Attributes See the register summary in Table 11-28 on page 11-41. Figure 11-26 shows the ROMPIDR4 bit assignments. Size DES_2 Figure 11-26 ROMPIDR4 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-48 ID021414 Non-Confidential...
Page 451 0xFF4 ROMCIDR2 0x05 0xFF8 ROMCIDR3 0xB1 0xFFC The Component Identification Registers identify Debug as an ARM Debug Interface v5 component. The ROM table Component ID registers are: • Component Identification Register • Component Identification Register 1 on page 11-50. •...
Page 452 The ROMCIDR1 is in the Debug power domain. Attributes See the register summary in Table 11-28 on page 11-41. Figure 11-28 shows the ROMCIDR1 bit assignments. CLASS PRMBL_1 Figure 11-28 ROMCIDR1 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-50 ID021414 Non-Confidential...
Page 453 The ROMCIDR2 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFF8 Component Identification Register 3 The ROMCIDR3 characteristics are: Purpose Provides information to identify an external debug component. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-51 ID021414 Non-Confidential...
Page 454 Name Function [31:8] Reserved, [7:0] PRMBL_3 Preamble byte 3. 0xB1 The ROMCIDR3 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFFC ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-52 ID021414 Non-Confidential...
Page 455 Memory-mapped register summary on page 12-23. • Memory-mapped register descriptions on page 12-26. • Events on page 12-36. • Interrupts on page 12-40. • Exporting PMU events on page 12-41. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-1 ID021414 Non-Confidential...
Page 456: Chapter 12 Performance Monitor Unit
12.1 About the PMU The Cortex-A53 processor includes performance monitors that implement the ARM PMUv3 architecture. These enable you to gather various statistics on the operation of the processor and its memory system during runtime. These provide useful information about the behavior of the processor that you can use when debugging or profiling code.
Page 457: Pmu Functional Description
External access to the performance monitor registers is also provided with the APB slave port. See External debug interface on page 11-37. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-3 ID021414 Non-Confidential...
Page 458 Stop at the first column whose condition is true, the entry gives the register access permission and scanning stops. Table 12-2 External register condition code example OSLK EPMAD Default RO/WI ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-4 ID021414 Non-Confidential...
Page 459: Aarch64 Pmu Register Summary
Execution state with instructions. Table 12-3 gives a summary of the Cortex-A53 PMU registers in the AArch64 Execution state. For those registers not described in this chapter, see the ARM Architecture Reference Manual ® ARMv8, for ARMv8-A architecture profile. Table 12-3 PMU register summary in the AArch64 Execution state...
Page 460 Table 12-3 PMU register summary in the AArch64 Execution state (continued) Name Type Width Description PMEVTYPER0_EL0 Performance Monitors Event Type Registers PMEVTYPER1_EL0 PMXVTYPER2_EL0 PMEVTYPER3_EL0 PMEVTYPER4_EL0 PMEVTYPER5_EL0 PMCCFILTR_EL0 Performance Monitors Cycle Count Filter Register ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-6 ID021414 Non-Confidential...
Page 461: Aarch64 Pmu Register Descriptions
Long cycle count enable. Determines which PMCCNTR_EL0 bit generates an overflow recorded in PMOVSR[31]. The possible values are: Overflow on increment that changes PMCCNTR_EL0[31] from 1 to 0. Overflow on increment that changes PMCCNTR_EL0[63] from 1 to 0. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-7 ID021414 Non-Confidential...
Page 462 No action. This is the reset value. Reset PMCCNTR_EL0 to 0. This bit is always RAZ. Note Resetting PMCCNTR does not clear the PMCCNTR_EL0 overflow bit to 0. See the ARM Architecture ® Reference Manual ARMv8, for ARMv8-A architecture profile. for more information.
Page 463 For each bit described in Table 12-6 on page 12-10, the event is implemented if the bit is set to 1, or not implemented if the bit is set to 0. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-9 ID021414 Non-Confidential...
Page 464 Data memory access: 0x13 This event is implemented. [18] BR_PRED Predictable branch speculatively executed: 0x12 This event is implemented. [17] CPU_CYCLES Cycle: 0x11 This event is implemented. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-10 ID021414 Non-Confidential...
Page 465 Instruction architecturally executed, condition check pass - software 0x00 increment: This event is implemented. To access the PMCEID0_EL0 in AArch64 Execution state, read or write the register with: ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-11 ID021414 Non-Confidential...
Page 466 For each bit described in Table 12-8 on page 12-13, the event is implemented if the bit is set to 1, or not implemented if the bit is set to 0. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-12 ID021414 Non-Confidential...
Page 467 MRS <Xt>, PMCEID1_EL0; Read Performance Monitor Common Event Identification Register 0 The PMCEID1_EL0 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xE24 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-13 ID021414 Non-Confidential...
Page 468: Aarch32 Pmu Register Summary
64-bit registers. MCRR MRRC Table 12-9 gives a summary of the Cortex-A53 PMU registers in the AArch32 Execution state. For those registers not described in this chapter, see the ARM Architecture Reference Manual ® ARMv8, for ARMv8-A architecture profile. See the...
Page 469 Table 12-9 PMU register summary in the AArch32 Execution state (continued) Name Type Width Description PMEVTYPER0 Performance Monitors Event Type Registers PMEVTYPER1 PMEVTYPER2 PMEVTYPER3 PMEVTYPER4 PMEVTYPER5 PMCCFILTR Performance Monitors Cycle Count Filter Register ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-15 ID021414 Non-Confidential...
Page 470: Aarch32 Pmu Register Descriptions
0x41 This is a read-only field. [23:16] IDCODE Identification code: Cortex-A53. 0x03 This is a read-only field. [15:11] Number of event counters. Six counters. 0b00110 [10:7] Reserved, ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-16 ID021414 Non-Confidential...
Page 471 No action. This is the reset value. Reset PMCCNTR_EL0 to 0. This bit is always RAZ. Note Resetting PMCCNTR does not clear the PMCCNTR_EL0 overflow bit to 0. See the ARM Architecture ® Reference Manual ARMv8, for ARMv8-A architecture profile for more information.
Page 472 Figure 12-6 PMCEID0 bit assignments Table 12-11 shows the PMCEID0 bit assignments with event implemented or not implemented when the associated bit is set to 1 or 0. See the ARM Architecture Reference Manual ARMv8, ® for ARMv8-A architecture profile for more information about these events.
Page 473 Data memory access: 0x13 This event is implemented. [18] BR_PRED Predictable branch speculatively executed: 0x12 This event is implemented. [17] CPU_CYCLES Cycle: 0x11 This event is implemented. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-19 ID021414 Non-Confidential...
Page 474 L1 Instruction cache refill: 0x01 This event is implemented. SW_INCR Instruction architecturally executed, condition check pass - software 0x00 increment: This event is implemented. To access the PMCEID0: ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-20 ID021414 Non-Confidential...
Page 475 12-14, the event is implemented if the bit is set to 1, or not implemented if the bit is set to 0. Table 12-14 PMU common events Event number Event mnemonic Description L2D_CACHE_ALLOCATE This event is not implemented. 0x20 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-21 ID021414 Non-Confidential...
Page 476 To access the PMCEID1: MRC p15,0,<Rt>,c9,c12,7 ; Read PMCEID1 into Rt The PMCEID1 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xE24 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-22 ID021414 Non-Confidential...
Page 477: Memory-Mapped Register Summary
Performance Monitor Count Enable Set Register 0xC00 Reserved 0xC04-0xC1C PMCNTENCLR_EL0 Performance Monitor Count Enable Clear Register 0xC20 Reserved 0xC24-0xC3C PMINTENSET_EL1 Performance Monitor Interrupt Enable Set Register 0xC40 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-23 ID021414 Non-Confidential...
Page 478 PMPIDR2 Peripheral Identification Register 2 on page 12-29 0xFE8 PMPIDR3 Peripheral Identification Register 3 on page 12-30 0xFEC PMCIDR0 Component Identification Register 0 on page 12-32 0xFF0 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-24 ID021414 Non-Confidential...
Page 479 0xFF8 PMCIDR3 Component Identification Register 3 on page 12-34 0xFFC a. This register is distinct from the PMCR_EL0 system register. It does not have the same value. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-25 ID021414 Non-Confidential...
Page 480: Memory-Mapped Register Descriptions
Dedicated cycle counter supported. The value is: Dedicated cycle counter is supported. [13:8] Size Counter size. The value is: 64-bit counters. 0b111111 [7:0] Number of event counters. The value is: Six counters. 0x06 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-26 ID021414 Non-Confidential...
Page 481 0xE00 12.8.2 Peripheral Identification Registers The Peripheral Identification Registers provide standard information required for all components that conform to the ARM PMUv3 architecture. There is a set of eight registers, listed in register number order in Table 12-17. Table 12-17 Summary of the Peripheral Identification Registers...
Page 482 The PMPIDR1 is in the Debug power domain. Attributes See the register summary in Table 12-15 on page 12-23. Figure 12-10 shows the PMPIDR1 bit assignments. DES_0 Part_1 Figure 12-10 PMPIDR1 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-28 ID021414 Non-Confidential...
Page 483 [31:8] Reserved, [7:4] DES_0 ARM Limited. This is the least significant nibble of JEP106 ID code. [3:0] Part_1 Most significant nibble of the performance monitor part number. The PMPIDR1 can be accessed through the internal memory-mapped interface and the external...
Page 484 The PMPIDR4 characteristics are: Purpose Provides information to identify a Performance Monitor component. Usage constraints The PMPIDR4 can be accessed through the internal memory-mapped interface and the external debug interface. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-30 ID021414 Non-Confidential...
Page 485 Size of the component. Log2 the number of 4KB pages from the start of the component to the end of the component ID registers. [3:0] DES_2 ARM Limited. This is the least significant nibble JEP106 continuation code. The PMPIDR4 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFD0 Peripheral Identification Register 5-7 No information is held in the Peripheral ID5, Peripheral ID6 and Peripheral ID7 Registers.
Page 486 Performance Monitor Unit The Component Identification Registers identify Performance Monitor as ARM PMUv3 architecture. The Component ID registers are: • Component Identification Register • Component Identification Register • Component Identification Register 2 on page 12-33. • Component Identification Register 3 on page 12-34.
Page 487 The PMCIDR2 is in the Debug power domain. Attributes See the register summary in Table 12-15 on page 12-23. Figure 12-16 on page 12-34 shows the PMCIDR2 bit assignments. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-33 ID021414 Non-Confidential...
Page 488 Figure 12-17 PMCIDR3 bit assignments Table 12-27 shows the PMCIDR3 bit assignments. Table 12-27 PMCIDR3 bit assignments Bits Name Function [31:8] Reserved, [7:0] PRMBL_3 Preamble byte 3. 0xB1 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-34 ID021414 Non-Confidential...
Page 489 Performance Monitor Unit The PMCIDR3 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFFC ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-35 ID021414 Non-Confidential...
Page 490: Events
L1 Data cache access. 0x13 L1I_CACHE [18] [18] L1 Instruction cache access. 0x14 L1D_CACHE_WB [19] [19] L1 Data cache Write-Back. 0x15 L2D_CACHE [20] [20] L2 Data cache access. 0x16 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-36 ID021414 Non-Confidential...
Page 491 L1 Instruction Cache (data or tag) 0xD0 memory error. [24] [24] L1 Data Cache (data, tag or dirty) 0xD1 memory error, correctable or non-correctable. [25] [25] TLB memory error. 0xD2 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-37 ID021414 Non-Confidential...
Page 492 Attributable Performance Impact Event 0xE7 Counts every cycle there is a stall in the Wr stage because of a load miss. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-38 ID021414 Non-Confidential...
Page 493 L2 (data or tag) memory error, correctable or non-correctable. [27] [27] SCU snoop filter memory error, correctable or non-correctable. [28] Advanced SIMD and Floating-point retention active. [29] CPU retention active. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-39 ID021414 Non-Confidential...
Page 494: 12.10 Interrupts
This is the only mechanism that signals this interrupt to the processor. This interrupt is also driven as a trigger input to the CTI. See Chapter 14 Cross Trigger for more information. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-40 ID021414 Non-Confidential...
Page 495: 12.11 Exporting Pmu Events
Cross Trigger Interface (CTI), to enable the events to be monitored. See Chapter 13 Embedded Trace Macrocell Chapter 14 Cross Trigger for more information. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-41 ID021414 Non-Confidential...
Page 496 ETM trace unit register interfaces on page 13-9. • ETM register summary on page 13-10. • ETM register descriptions on page 13-13. • Interaction with debug and performance monitoring unit on page 13-76. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-1 ID021414 Non-Confidential...
Page 497: Chapter 13 Embedded Trace Macrocell
The ETM trace unit is a module that performs real-time instruction flow tracing based on the Embedded Trace Macrocell (ETM) architecture ETMv4. ETM is a CoreSight component, and is an integral part of the ARM Real-time Debug solution, DS-5 Development Studio. See the CoreSight documentation in Additional reading on page ix for more information.
Page 498: Etm Trace Unit Generation Options And Resources
Number of cores available for tracing ATB trigger support Implemented Low power behavior override Implemented Stall control support Implemented Support for no overflows in the trace Not implemented ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-3 ID021414 Non-Confidential...
Page 499 Number of address comparator pairs implemented Number of single-shot comparator controls Number of processor comparator inputs implemented Data address comparisons implemented Not implemented Number of data value comparators implemented ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-4 ID021414 Non-Confidential...
Page 500: Etm Trace Unit Functional Description
When the FIFO becomes full, the FIFO signals an overflow. The trace generation logic does not generate any new trace until the FIFO is emptied. This causes a gap in the trace when viewed in the debugger. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-5 ID021414 Non-Confidential...
Page 501 Trace from FIFO is output on the synchronous AMBA ATB interface. 13.3.6 Syncbridge The ATB interface from the trace out block goes through an ATB synchronous bridge. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-6 ID021414 Non-Confidential...
Page 502: Reset
If the ETM trace unit is reset, tracing stops until the ETM trace unit is reprogrammed and re-enabled. However, if the processor is reset using warm reset, the last few instructions provided by the processor before the reset might not be traced. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-7 ID021414 Non-Confidential...
Page 503: Modes Of Operation And Execution
Programming and reading ETM trace unit registers You program and read the ETM trace unit registers using the Debug APB interface. This provides a direct method of programming the ETM trace unit. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-8 ID021414 Non-Confidential...
Page 504: Etm Trace Unit Register Interfaces
Access permissions See the ARM Architecture Specification, ETMv4 for information on the behaviors on ® ™ register accesses for different trace unit states and the different access mechanisms. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-9 ID021414 Non-Confidential...
Page 505: Etm Register Summary
Sequencer State Transition Control Registers 0-2 on page 13-27 TRCSEQEVR2 Sequencer State Transition Control Registers 0-2 on page 13-27 TRCSEQRSTEVR Sequencer Reset Control Register on page 13-28 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-10 ID021414 Non-Confidential...
Page 506 Context ID Comparator Value Register 0 on page 13-54 TRCVMIDCVR0 VMID Comparator Value Register 0 on page 13-54 TRCCIDCCTLR0 Context ID Comparator Control Register 0 on page 13-55 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-11 ID021414 Non-Confidential...
Page 507 Component Identification Register 0 on page 13-72 TRCCIDR1 Component Identification Register 1 on page 13-73 TRCCIDR2 Component Identification Register 2 on page 13-74 TRCCIDR3 Component Identification Register 3 on page 13-74 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-12 ID021414 Non-Confidential...
Page 508: Etm Register Descriptions
Usage constraints There are no usage constraints. Configurations Available in all configurations. Attributes See the register summary in Table 13-3 on page 13-10. Figure 13-4 on page 13-14 shows the TRCSTATR bit assignments. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-13 ID021414 Non-Confidential...
Page 509 See the register summary in Table 13-3 on page 13-10. Figure 13-5 shows the TRCCONFIGR bit assignments. 12 11 10 5 4 3 2 VMID Figure 13-5 TRCCONFIGR bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-14 ID021414 Non-Confidential...
Page 510 Must be programmed if TRCCONFIGR.BB == 1. Configurations Available in all configurations. Attributes See the register summary in Table 13-3 on page 13-10. Figure 13-6 on page 13-16 shows the TRCBBCTLR bit assignments. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-15 ID021414 Non-Confidential...
Page 511 Usage constraints There are no usage constraints. Configurations Available in all configurations. Attributes See the register summary in Table 13-3 on page 13-10. Figure 13-7 on page 13-17 shows the TRCAUXCTLR bit assignments. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-16 ID021414 Non-Confidential...
Page 512 Delay periodic synchronization if FIFO is more than half-full. The possible values are: SYNC packets are inserted into FIFO only when trace activity is low. SYNC packets are inserted into FIFO irrespective of trace activity. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-17 ID021414 Non-Confidential...
Page 513 TRCEVENTCTL0R bit assignments. 28 27 24 23 22 20 19 16 15 14 12 11 SEL3 SEL2 SEL1 SEL0 TYPE3 TYPE2 TYPE1 TYPE0 Figure 13-8 TRCEVENTCL0R bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-18 ID021414 Non-Confidential...
Page 514 You must always program this register as part of trace unit initialization. • Accepts writes only when the trace unit is disabled. Configurations Available in all configurations. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-19 ID021414 Non-Confidential...
Page 515 Accepts writes only when the trace unit is disabled. Configurations Available in all configurations. Attributes See the register summary in Table 13-3 on page 13-10. Figure 13-10 on page 13-21 shows the TRCSTALLCTLR bit assignments. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-20 ID021414 Non-Confidential...
Page 516 See also UNKNOWN Table 13-3 on page 13-10. Figure 13-11 shows the TRCTSCTLR bit assignments: TYPE Figure 13-11 TRCTSCTLR bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-21 ID021414 Non-Confidential...
Page 517 The maximum value is 20, providing a maximum synchronization period of 2 bytes. The TRCSYNCPR can be accessed through the internal memory-mapped interface and the external debug interface, offset 0x034 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-22 ID021414 Non-Confidential...
Page 518 TRCTRACEIDR is a 32-bit RW trace register. See the register summary in Table 13-3 on page 13-10. Figure 13-14 shows the TRCTRACEIDR bit assignments. TRACEID Figure 13-14 TRCTRACEIDR bit Assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-23 ID021414 Non-Confidential...
Page 519 See the register summary in Table 13-3 on page 13-10. Figure 13-15 shows the TRCVICTLR bit assignments. EXLEVEL_S TYPE EXLEVEL_NS SSSTATUS TRCRESET TRCERR Figure 13-15 TRCVICTLR bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-24 ID021414 Non-Confidential...
Page 520 Reset exception is always traced regardless of the value of ViewInst. SSSTATUS Indicates the current status of the start/stop logic: Start/stop logic is in the stopped state. Start/stop logic is in the started state. Reserved, ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-25 ID021414 Non-Confidential...
Page 521 Selecting no include comparators indicates that all instructions must be included. The exclude control indicates which ranges must be excluded. One bit is provided for each implemented Address Range Comparator. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-26 ID021414 Non-Confidential...
Page 522 Returns stable data only when TRCSTATR.PMSTABLE==1. • Software must use this register to set the initial state of the sequencer before the sequencer is used. Configurations Available in all configurations. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-27 ID021414 Non-Confidential...
Page 523 If the sequencer is used, you must program all sequencer state transitions with a valid event. Configurations Available in all configurations. Attributes See the register summary in Table 13-3 on page 13-10. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-28 ID021414 Non-Confidential...
Page 524 Available in all configurations. Attributes See the register summary in Table 13-3 on page 13-10. Figure 13-20 shows the TRCSEQSTR bit assignments. STATE Figure 13-20 TRCSEQSTR bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-29 ID021414 Non-Confidential...
Page 525 Selects an event from the external input bus for External Input Resource 1. [7:5] Reserved, [4:0] SEL0 Selects an event from the external input bus for External Input Resource 0. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-30 ID021414 Non-Confidential...
Page 526 Table 13-3 on page 13-10. Figure 13-23 shows the TRCCNTCTLR0 bit assignments. 16 15 14 12 11 8 7 6 RLDSEL CNTSEL RLDSELF CNTTYPE RLDTYPE Figure 13-23 TRCCNTCTLR0 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-31 ID021414 Non-Confidential...
Page 527 13-10. Figure 13-24 shows the TRCCNTCTLR1 bit assignments. 16 15 14 12 11 8 7 6 RLDSEL CNTSEL CNTCHAIN CNTTYPE RLDSELF RLDTYPE Figure 13-24 TRCCNTCTLR1 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-32 ID021414 Non-Confidential...
Page 528 If software uses counter <n>, then it must write to this register to set the initial counter value. Configurations Available in all configurations. Attributes See the register summary in Table 13-3 on page 13-10. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-33 ID021414 Non-Confidential...
Page 529 The maximum number of P0 elements in the trace stream that can be speculative at any time. Maximum speculation depth of the instruction trace stream. The TRCIDR8 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0x180 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-34 ID021414 Non-Confidential...
Page 530 Available in all configurations. Attributes See the register summary in Table 13-3 on page 13-10. Figure 13-28 shows the TRCIDR10 bit assignments. NUMP1KEY Figure 13-28 TRCIDR10 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-35 ID021414 Non-Confidential...
Page 531 Usage constraints There are no usage constraints. Configurations Available in all configurations. Attributes See the register summary in Table 13-3 on page 13-10. Figure 13-30 on page 13-37 shows the TRCIDR12 bit assignments. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-36 ID021414 Non-Confidential...
Page 532 Number of special conditional instruction right-hand keys. The TRCIDR13 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0x194 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-37 ID021414 Non-Confidential...
Page 533 Usage constraints There are no usage constraints. Configurations Available in all configurations. Attributes See the register summary in Table 13-3 on page 13-10. Figure 13-33 on page 13-39 shows the TRCIDR0 bit assignments. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-38 ID021414 Non-Confidential...
Page 534 Tracing of data addresses and data values is not implemented. 0b00 [2:1] INSTP0 P0 tracing support field: Tracing of load and store instructions as P0 elements is not supported. 0b00 Reserved, ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-39 ID021414 Non-Confidential...
Page 535 The TRCIDR2 characteristics are: Purpose Returns the maximum size of the following parameters in the trace unit: • Cycle counter. • Data value. • Data address. • VMID. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-40 ID021414 Non-Confidential...
Page 536 The number of cores available for tracing. • If an exception level supports instruction tracing. • The minimum threshold value for instruction trace cycle counting. • Whether the synchronization period is fixed. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-41 ID021414 Non-Confidential...
Page 537 Each bit controls whether instruction tracing in Non-secure state is implemented for the corresponding exception level: Instruction tracing is implemented for Non-secure EL0, EL1 and EL2 exception levels. 0b0111 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-42 ID021414 Non-Confidential...
Page 538 Indicates the number of resource selection pairs available for tracing: Eight resource selection pairs are available. [15:12] NUMPC Indicates the number of processor comparator inputs available for tracing: Processor comparator inputs are not implemented. [11:9] Reserved, ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-43 ID021414 Non-Confidential...
Page 539 Reduced Function Counter not implemented. [30:28] NUMCCNTR Number of counters implemented: Two counters implemented. b010 [27:25] NUMSEQSTATE Number of sequencer states implemented: Four sequencer states implemented. b100 [24] Reserved, ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-44 ID021414 Non-Confidential...
Page 540 See the register summary in Table 13-3 on page 13-10. Figure 13-39 shows the TRCRSCTLRn bit assignments. 22 21 20 19 16 15 Group Select PAIRINV Figure 13-39 TRCRSCTLRn bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-45 ID021414 Non-Confidential...
Page 541 [20] Inverts the selected resources: Resource is not inverted. Resource is inverted. [19] Reserved, [18:16] GROUP Selects a group of resources. See the ARM Architecture Specification, ETMv4 for more information. ® ™ [15:8] Reserved, [7:0] SELECT Selects one or more resources from the required group. One bit is provided for each resource from the group.
Page 542 When programming the ETM trace unit, if TRCSSCCRn.RST is b0, the STATUS bit must be explicitly written to 0 to enable this single-shot comparator control. [30:3] Reserved, ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-47 ID021414 Non-Confidential...
Page 543 The TRCOSLAR can be accessed through the internal memory-mapped interface and the external debug interface, offset 0x300 13.8.41 OS Lock Status Register The TRCOSLSR characteristics are: Purpose Returns the status of the OS Lock. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-48 ID021414 Non-Confidential...
Page 544 Usage constraints There are no usage constraints. Configurations Available in all configurations. Attributes See the register summary in Table 13-3 on page 13-10. Figure 13-44 on page 13-50 shows the TRCPDCR bit assignments. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-49 ID021414 Non-Confidential...
Page 545 See the register summary in Table 13-3 on page 13-10. Figure 13-45 shows the TRCPDSR bit assignments. 6 5 4 2 1 0 OSLK STICKYPD POWER Figure 13-45 TRCPDSR bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-50 ID021414 Non-Confidential...
Page 546 Figure 13-46 TRCACVRn bit assignments Table 13-47 shows the TRCACVRn bit assignments. Table 13-47 TRCACVRn bit assignments Bits Name Function [63:0] ADDRESS The address value to compare against. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-51 ID021414 Non-Confidential...
Page 547 Table 13-3 on page 13-10. Figure 13-47 shows the TRCACATRn bit assignments. 16 15 12 11 3 2 1 0 TYPE EXLEVEL_NS CONTEXTTYPE EXLEVEL_S Figure 13-47 TRCACATRn bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-52 ID021414 Non-Confidential...
Page 548 VMID comparator matches, and the address comparator matches. [1:0] Type The type of comparison: Instruction address, The TRCACATRn can be accessed through the internal memory-mapped interface and the external debug interface, offset 0x480-0x4B8 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-53 ID021414 Non-Confidential...
Page 549 Available in all configurations. Attributes See the register summary in Table 13-3 on page 13-10. Figure 13-49 shows the TRCVMIDCVR0 bit assignments. VALUE Figure 13-49 TRCVMIDCVR0 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-54 ID021414 Non-Confidential...
Page 550 The trace unit ignores the relevant byte in TRCCIDCVR0 when it performs the Context ID comparison. The TRCCIDCCTLR0 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0x680 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-55 ID021414 Non-Confidential...
Page 551 Configurations Available in all configurations. Attributes See the register summary in Table 13-3 on page 13-10. Figure 13-52 on page 13-57 shows the TRCITIDATAR bit assignments. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-56 ID021414 Non-Confidential...
Page 552 The TRCITDDATAR bit values correspond to the physical state of the output pins. The TRCITIDATAR can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xEEC ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-57 ID021414 Non-Confidential...
Page 553 The TRCITIATBINR bit values always correspond to the physical state of the input pins. The TRCITIATBINR can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xEF4 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-58 ID021414 Non-Confidential...
Page 554 The TRCITCTRL characteristics are: Purpose Enables topology detection or integration testing, by putting the ETM trace unit into integration mode. Usage constraints ARM recommends that you perform a debug reset after using integration mode. Configurations Available in all configurations. ARM DDI 0500D Copyright ©...
Page 555 Available in all configurations. Attributes See the register summary in Table 13-3 on page 13-10. Figure 13-56 shows the TRCCLAIMSET bit assignments. Figure 13-56 TRCCLAIMSET bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-60 ID021414 Non-Confidential...
Page 556 Has no effect. Clears the relevant bit of the claim tag. The TRCCLAIMCLR can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFA4 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-61 ID021414 Non-Confidential...
Page 557 TRCDEVAFF0 is a 32-bit register. Figure 13-58 shows the TRCDEVAFF0 bit assignments. 31 30 29 25 24 16 15 Aff2 Aff1 Aff0 Figure 13-58 TRCDEVAFF0 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-62 ID021414 Non-Confidential...
Page 558 Usage constraints Accessible only from the memory-mapped interface or the external debugger interface. Configurations Available in all configurations. Attributes TRCDEVAFF1 is a 32-bit RO management register. For the Cortex-A53 processor, MPIDR_EL1[63:32] is ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-63 ID021414 Non-Confidential...
Page 559 Usage constraints Accessible only from the memory-mapped interface or the external debugger interface. Configurations Available in all configurations. Attributes See the register summary in Table 13-3 on page 13-10. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-64 ID021414 Non-Confidential...
Page 560 Available in all configurations. Attributes See the register summary in Table 13-3 on page 13-10 Figure 13-61 shows the TRCAUTHSTATUS bit assignments. SNID NSNID NSID Figure 13-61 TRCAUTHSTATUS bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-65 ID021414 Non-Confidential...
Page 561 See the register summary in Table 13-3 on page 13-10. Figure 13-62 shows the TRCDEVARCH bit assignments. 21 20 19 16 15 ARCHITECT REVISION ARCHID PRESENT Figure 13-62 TRCDEVARCH bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-66 ID021414 Non-Confidential...
Page 562 The TRCDEVID can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFC8 13.8.63 Device Type Register The TRCDEVTYPE characteristics are: Purpose Indicates the type of the component. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-67 ID021414 Non-Confidential...
Page 563 Peripheral ID3 0x00 0xFEC Only bits[7:0] of each Peripheral ID Register are used, with bits[31:8] reserved. Together, the eight Peripheral ID Registers define a single 64-bit Peripheral ID. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-68 ID021414 Non-Confidential...
Page 564 TRCPIDR1 is a 32-bit RO management register. See the register summary in Table 13-3 on page 13-10. Figure 13-66 on page 13-70 shows the TRCPIDR1 bit assignments. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-69 ID021414 Non-Confidential...
Page 565 Function [31:8] Reserved, [7:4] DES_0 ARM Limited. This is bits [3:0] of JEP106 ID code. [3:0] Part_1 Most significant four bits of the ETM trace unit part number. The TRCPIDR1 can be accessed through the internal memory-mapped interface and the...
Page 566 TRCPIDR4 is a 32-bit RO management register. See the register summary in Table 13-3 on page 13-10. Figure 13-69 on page 13-72 shows the TRCPIDR4 bit assignments. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-71 ID021414 Non-Confidential...
Page 567 Size of the component. Log2 the number of 4KB pages from the start of the component to the end of the component ID registers. [3:0] DES_2 ARM Limited. This is bits [3:0] of the JEP106 continuation code. The TRCPIDR4 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFD0 Peripheral Identification Register 5-7 No information is held in the Peripheral ID5, Peripheral ID6 and Peripheral ID7 Registers.
Page 568 Available in all implementations. Attributes See the register summary in Table 13-3 on page 13-10. Figure 13-71 shows the TRCCIDR1 bit assignments. CLASS PRMBL_1 Figure 13-71 TRCCIDR1 bit assignments ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-73 ID021414 Non-Confidential...
Page 569 Purpose Provides information to identify a trace component. Usage constraints • Only bits[7:0] are valid. • Accessible only from the memory-mapped interface or the external debugger interface. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-74 ID021414 Non-Confidential...
Page 570 Name Function [31:8] Reserved, [7:0] PRMBL_3 Preamble byte 3. 0xB1 The TRCCIDR3 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFFC ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-75 ID021414 Non-Confidential...
Page 571: Interaction With Debug And Performance Monitoring Unit
All trace register accesses through the memory-mapped and external debug interfaces behave as if the processor power domain is powered down when debug double lock is set. For more information on debug double lock, see the ARM Architecture Reference Manual ARMv8, for ®...
Page 572: Chapter 14 Cross Trigger
Trigger inputs and outputs on page 14-3. • Cortex-A53 CTM on page 14-4. • Cross trigger register summary on page 14-5. • Cross trigger register descriptions on page 14-8. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 14-1 ID021414 Non-Confidential...
Page 573: About The Cross Trigger
CTIIRQ CTIIRQACK EXTIN[3:0] EXTOUT[3:0] Debug request Debug trigger Debug restart nCOMMIRQ Debug COMMRX COMMTX CTICHOUT CTICHOUTACK CTICHIN CTICHINACK nCOMMIRQ COMMRX COMMTX EDBGRQ Figure 14-1 Debug system components ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 14-2 ID021414 Non-Confidential...
Page 574: Trigger Inputs And Outputs
CTIIRQ CTI interrupt EXTIN[0] ETM trace unit external input EXTIN[1] ETM trace unit external input EXTIN[2] ETM trace unit external input EXTIN[3] ETM trace unit external input ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 14-3 ID021414 Non-Confidential...
Page 575: Cortex-A53 Ctm
In the simplified CTM, external channel output is driven by the OR output of all internal channel outputs. Each internal channel input is driven by the OR output of internal channel outputs of all other CTIs in addition to the external channel input. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 14-4 ID021414 Non-Confidential...
Page 576: Cross Trigger Register Summary
Table 14-3 gives a summary of the Cortex-A53 cross trigger registers. For those registers not described in this chapter, see the ARM Architecture Reference Manual ARMv8, for ARMv8-A ®...
Page 577 CTICIDR1 Component Identification Register 1 on page 14-15 0xFF4 CTICIDR2 Component Identification Register 2 on page 14-16 0xFF8 CTICIDR3 Component Identification Register 3 on page 14-17 0xFFC ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 14-6 ID021414 Non-Confidential...
Page 578 Stop at the first column a condition is true, the entry gives the access permission of the register and scanning stops. Table 14-5 External register condition code example OSLK EDAD Default RO/WI ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 14-7 ID021414 Non-Confidential...
Page 579: Cross Trigger Register Descriptions
Cross Trigger 14.5 Cross trigger register descriptions This section describes the Cortex-A53 MPCore Cross Trigger registers. The Cross trigger register summary on page 14-5 provides cross-references to the individual registers. 14.5.1 CTI Device Identification Register The CTIDEVID characteristics are: Purpose Describes the CTI component to the debugger.
Page 580 [31:1] Reserved, Integration mode enable. The possible value is: Normal operation. CTIITCTRL can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xF00 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 14-9 ID021414 Non-Confidential...
Page 581 Cross Trigger 14.5.3 CTI Peripheral Identification Registers The Peripheral Identification Registers provide standard information required for all components that conform to the ARM CoreSight architecture. There is a set of eight registers, listed in register number order in Table 14-8.
Page 582 Bits Name Function [31:8] Reserved, [7:4] DES_0 ARM Limited. This is the least significant nibble of JEP106 ID code. [3:0] Part_1 Most significant nibble of the CTI part number. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 14-11...
Page 583 JEDEC 1. Indicates a JEP106 identity code is used. [2:0] DES_1 ARM Limited. This is the most significant nibble of JEP106 ID code. 0b011 CTIPIDR2 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFE8...
Page 584 CTIPIDR4 is optional to implement in the external register interface. Attributes See the register summary in Table 14-3 on page 14-5. Figure 14-8 on page 14-14 shows the CTIPIDR4 bit assignments. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 14-13 ID021414 Non-Confidential...
Page 585 Size of the component. Log2 the number of 4KB pages from the start of the component to the end of the component ID registers. [3:0] DES_2 ARM Limited. This is the least significant nibble JEP106 continuation code. CTIPIDR4 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFD0 Peripheral Identification Register 5-7 No information is held in the Peripheral ID5, Peripheral ID6, and Peripheral ID7 Registers.
Page 586 CTICIDR1 is optional to implement in the external register interface. Attributes See the register summary in Table 14-3 on page 14-5. Figure 14-10 on page 14-16 shows the CTICIDR1 bit assignments. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 14-15 ID021414 Non-Confidential...
Page 587 Figure 14-11 CTICIDR2 bit assignments Table 14-17 shows the CTICIDR2 bit assignments. Table 14-17 CTICIDR2 bit assignments Bits Name Function [31:8] Reserved, [7:0] PRMBL_2 Preamble byte 2. 0x05 ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 14-16 ID021414 Non-Confidential...
Page 588 Bits Name Function [31:8] Reserved, [7:0] PRMBL_3 Preamble byte 3. 0xB1 CTICIDR3 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFFC ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 14-17 ID021414 Non-Confidential...
Page 589: Appendix A Signal Descriptions
Miscellaneous ETM trace unit signals on page A-29. • CTI interface signals on page A-30. • PMU interface signals on page A-31. • DFT and MBIST interface signals on page A-32. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 590: About The Signal Descriptions
The number of signals changes depending on the configuration. For example, the AMBA 5 CHI interface signals are not present when the processor is configured to have an AMBA 4 ACE interface. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 591: Clock Signals
Signal Descriptions Clock signals Table A-1 shows the clock signal. Table A-1 Clock signal Signal Direction Description CLKIN Input Global clock ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 592: Reset Signals
Processor logic includes Advanced SIMD and Floating-point, but excludes Debug, ETM trace unit, breakpoint and watchpoint logic. Note • See nPRESETDBG in Table A-34 on page A-25. • See nMBISTRESET in Table A-41 on page A-32. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 593: Configuration Signals
Location of the exception vectors at reset. It sets the initial value of the V bit in the CP15 SCTLR register: Exception vectors start at address 0x00000000 Exception vectors start at address 0xFFFF0000 This pin is sampled only during reset of the processor. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 594: Generic Interrupt Controller Signals
Virtual CPU interface maintenance interrupt PPI output. PERIPHBASE[39:18] Input Specifies the base address for the GIC registers. This value is sampled into the CP15 Configuration Base Address Register (CBAR) at reset. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 595 Globally disables the CPU interface logic and routes the “External” signals directly to the processor: Enable the GIC CPU interface logic. Disable the GIC CPU interface logic. Required to enable use of non-ARM interrupt controllers. ICDTVALID Input AXI4 Stream Protocol signal. Distributor to GIC CPU Interface messages. TVALID indicates that the master is driving a valid transfer.
Page 596: Generic Timer Signals
Virtual physical timer event. CNTCLKEN Input Counter clock enable. This clock enable must be inserted one cycle before the CNTVALUEB bus. CNTVALUEB[63:0] Input Global system counter value in binary format. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 597: Power Management Signals
Request that the processor is not powered up. DBGPWRDUP[CN:0] Input Processor powered up Processor is powered down. Processor is powered up. Table A-7 on page A-10 shows the Retention power management signals. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 598 Output Indicates that the L2 data RAMs deny the power controller retention request L2QACCEPTn Output Indicates that the L2 data RAMs accept the power controller retention request ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. A-10 ID021414 Non-Confidential...
Page 599: L2 Error Signals
Error indicator for AXI or CHI transactions with a write response error condition. External aborts handling on page 7-18 for more information. nINTERRIRQ Output Error indicator for L2 RAM double-bit ECC error. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. A-11 ID021414 Non-Confidential...
Page 600: Ace And Chi Interface Signals
Outer Shareable transactions are broadcast externally. This pin is sampled only during reset of the Cortex-A53 processor. a. See Table 7-1 on page 7-3 for more information. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. A-12 ID021414 Non-Confidential...
Page 601: Chi Interface Signals
Direction Description TXREQFLITPEND Output Transmit request flit pending TXREQFLITV Output Transmit request flit valid TXREQFLIT[99:0] Output Transmit request flit payload TXREQLCRDV Input Transmit request link-layer credit valid ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. A-13 ID021414 Non-Confidential...
Page 602 A.10.6 Receive response virtual channel signals Table A-15 shows the receive response virtual channel signals. Table A-15 Receive response virtual channel signals Signal Direction Description RXRSPFLITPEND Input Receive response flit pending ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. A-14 ID021414 Non-Confidential...
Page 603 Input Region mapping, 32GB – 64GB SAMADDRMAP12[1:0] Input Region mapping, 64GB – 128GB SAMADDRMAP13[1:0] Input Region mapping, 128GB – 256GB SAMADDRMAP14[1:0] Input Region mapping, 256GB – 512GB ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. A-15 ID021414 Non-Confidential...
Page 604 HN-F 6 node ID SAMHNF7NODEID[6:0] Input HN-F 7 node ID SAMHNFMODE[2:0] Input HN-F interleaving module a. SAMMNBASE must reside in a SAMADDRMAPx[1:0] that corresponds to the HN-I. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. A-16 ID021414 Non-Confidential...
Page 605: Ace Interface Signals
Coherency data channel handshake signals on page A-21. • Read and write acknowledge signals on page A-21. For a complete description of the ACE interface signals, see the ARM AMBA AXI and ACE ® ® Protocol Specification AXI3, AXI4, and AXI4-Lite, ACE and ACE-Lite.
Page 606 WIDM[4:0] Output Write data ID WLASTM Output Write data last transfer indication WREADYM Input Write data ready WSTRBM[15:0] Output Write byte-lane strobes WVALIDM Output Write data valid ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. A-18 ID021414 Non-Confidential...
Page 607 Read lock type. ARPROTM[2:0] Output Read protection type. ARREADYM Input Read address ready. ARSIZEM[2:0] Output Read burst size. ARSNOOPM[3:0] Output Read snoop request type. ARVALIDM Output Read address valid. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. A-19 ID021414 Non-Confidential...
Page 608 ACE master interface. Table A-25 Coherency response channel signals Signal Direction Description CRREADYM Input Slave ready to accept snoop response CRVALIDM Output Snoop response CRRESPM[4:0] Output Snoop response valid ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. A-20 ID021414 Non-Confidential...
Page 609 ACE master interface. Table A-27 Read and write acknowledge signals Signal Direction Description RACKM Output Read acknowledge WACKM Output Write acknowledge ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. A-21 ID021414 Non-Confidential...
Page 610: Acp Interface Signals
Signal Direction Description AWREADYS Output Write address ready AWVALIDS Input Write address valid AWIDS[4:0] Input Write address ID AWADDRS[39:0] Input Write address AWLENS[7:0] Input Write burst length ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. A-22 ID021414 Non-Confidential...
Page 611 Table A-32 Read address channel signals Signal Direction Description ARREADYS Output Read address ready ARVALIDS Input Read address valid ARIDS[4:0] Input Read address ID ARADDRS[39:0] Input Read address ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. A-23 ID021414 Non-Confidential...
Page 612 Read data ready RVALIDS Output Read data valid RIDS[4:0] Output Read data ID RDATAS[127:0] Output Read data RRESPS[1:0] Output Read response RLASTS Output Read data last transfer indication ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. A-24 ID021414 Non-Confidential...
Page 613: External Debug Interface
PWRITEDBG Input APB read or write signal: Reads from APB. Writes to APB. A.13.2 Miscellaneous debug signals Table A-35 on page A-26 shows the miscellaneous Debug signals. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. A-25 ID021414 Non-Confidential...
Page 614 No powerdown request: On a powerdown request, the SoC power controller powers down the processor. On a powerdown request, the SoC power controller does not power down the processor. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. A-26 ID021414 Non-Confidential...
Page 615 Enable automatic invalidation of L1 data cache on reset. Disable automatic invalidation of L1 data cache on reset. This pin is sampled only during reset of the processor. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. A-27 ID021414 Non-Confidential...
Page 616: Atb Interface Signals
ATB device ready AFVALIDMx Input FIFO flush request ATDATAMx[31:0] Output Data ATVALIDMx Output Data valid ATBYTESMx[1:0] Output Data size AFREADYMx Output FIFO flush finished ATIDMx[6:0] Output Trace source ID ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. A-28 ID021414 Non-Confidential...
Page 617: Miscellaneous Etm Trace Unit Signals
ETM trace unit signals. Table A-37 Miscellaneous ETM trace unit signals Signal Direction Description SYNCREQMx Input Synchronization request from trace sink TSVALUEB[63:0] Input Timestamp in binary encoding ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. A-29 ID021414 Non-Confidential...
Page 618: Cti Interface Signals
CTICHINACK[3:0] Output Channel In acknowledge CISBYPASS Input Channel interface sync bypass CIHSBYPASS[3:0] Input Channel interface H/S bypass CTIIRQ[CN:0] Output CTI interrupt (active-HIGH) CTIIRQACK[CN:0] Input CTI interrupt acknowledge ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. A-30 ID021414 Non-Confidential...
Page 619: Pmu Interface Signals
PMU interface signals Table A-39 shows the PMU interface signals. Table A-39 PMU interface signals Signal Direction Description PMUEVENTx[29:0] Output PMU event bus nPMUIRQ[CN:0] Output PMU interrupt request ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. A-31 ID021414 Non-Confidential...
Page 620: Dft And Mbist Interface Signals
MBIST into the design before synthesis. The process of adding MBIST into the design can be done automatically by an EDA MBIST tool. Table A-41 MBIST interface signals Signal Direction Description MBISTREQ Input MBIST test request nMBISTRESET Input MBIST reset ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. A-32 ID021414 Non-Confidential...
Page 621: Use Of R15 By Instruction
Where possible and practical, all ARM implementations adhere to these single preferred behaviors. In some limited instances an ARM implementation might not adhere to these single preferred behaviors, and instead behaves as described by one of the alternate legal behaviors.
Page 622: Load/Store Accesses Crossing Page Boundaries
Cortex-A53 Processor AArch32 unpredictable Behaviors • Load/Store accesses crossing page boundaries on page B-5. • ARMv8 Debug unpredictable behaviors on page B-6. • Other unpredictable behaviors on page B-11. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 623: B.1 Use Of R15 By Instruction
ARM Architecture Reference Manual ARMv8, for ARMv8-A ® UNPREDICTABLE architecture profile pseudo-code, or in other places in the ARM Architecture Reference Manual ® ARMv8, for ARMv8-A architecture profile, read 0 unless otherwise stated in section 4.28, or as described in the following paragraph.
Page 624 The Cortex-A53 processor does not implement an unconditional execution policy for the following instructions. Instead all execute conditionally: • NEON instructions new to ARMv8. • All instructions in the ARMv8 Cryptographic Extensions. • CRC32. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 625: B.3 Load/Store Accesses Crossing Page Boundaries
Device->Device and Normal->Normal. No fault, load is split into two accesses. Each access behaves according to the attributes of the page that each load hits. — Device->Normal and Normal->Device. Results in an alignment fault. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 626 Mismatch breakpoint on branch to self The Cortex-A53 processor implements: • Option 2: Instruction is stepped an number of times, while it continues to UNKNOWN branch to itself. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 627 B.4.16 Execute instruction at a given EL when the corresponding EDECCR bit is 1 and Halting is allowed The Cortex-A53 processor behaves as follows: • Generates debug event and Halt no later than the instruction following the next Context Synchronization operation (CSO) excluding ISB instruction. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 628 B.4.22 P ≥ M and P ≠ 31: value read in PMSELR_EL0.SEL The Cortex-A53 processor implements: • A simple implementation where all of SEL[4:0] are implemented, and if P ≥ M and P ≠ 31 then the register is ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 629 Core power domain is either completely off, or in a low-power state where the Core power domain registers cannot be accessed. is TRUE, OS double-lock is locked, that is, DoubleLockStatus() EDPRSR.DLK is 1). OSLK OSLSR_EL1.OSLK is1, OS lock is locked. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 630 B.4.31 Clearing the clear-after-read EDPRSR bits when Core power domain is on, and DoubleLockStatus() is TRUE The Cortex-A53 processor behaves as indicated in the sole Preference: • Bits are not cleared to zero. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. B-10 ID021414 Non-Confidential...
Page 631 (The value that was written to HDCR.HPMN) modulo 2h, where h is the smallest number of bits required for a value in the range 0 to PMCR.N. ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. B-11 ID021414 Non-Confidential...
Page 632: Appendix C Revisions
Peripheral Identification Register 2 on page 14-12 Peripheral Identification Register 2 on page 11-47 ID_AA64MMFR0_EL1 description updated AArch64 Memory Model Feature Register 0, EL1 on page 4-41 All revisions ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 633 All revisions Updated CPUMERRSR descriptions Table 4-147 on page 4-156 Table 4-246 on page 4-275 Removed DACR from list of c4 registers c4 registers on page 4-139 All revisions ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 634 Device Affinity Register 0 on page 13-62 All revisions description updated to match MPIDR Updated sequence of operations in section 11.10.4 (Changing All revisions Changing the authentication signals on page 11-40 the authentication signals) ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...
Page 635 Table 13-22 on page 13-30 Updated number of external inputs to trace unit Table 13-39 on page 13-44 All revisions Footnote added to SAMMNBASE[39,24] Table A-17 on page A-15 All revisions description ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ID021414 Non-Confidential...

ARM Cortex-A53 MPCore Technical Reference Manual

Preface

Chapter 1 Introduction

Chapter 2 Functional Description

Chapter 3 Programmers Model

Chapter 4 System Control

Chapter 5 Memory Management Unit

Chapter 6 Level 1 Memory System

Chapter 7 Level 2 Memory System

Chapter 8 Cache Protection

Chapter 9 Generic Interrupt Controller CPU Interface

Chapter 10 Generic Timer

Chapter 11 Debug

Chapter 12 Performance Monitor Unit

Chapter 13 Embedded Trace Macrocell

Chapter 14 Cross Trigger

Appendix A Signal Descriptions

Appendix B Cortex-A53 Processor Aarch32 Unpredictable Behaviors

Appendix C Revisions

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