Samsung S5PC110 Manual page 319

S5PC110_UM
3.7.2.3 PLL Control Registers (EPLL_CON0/ EPLL_CON1, R/W, Address = 0xE010_0110/0xE010_0114)
EPLL_CON0
ENABLE
Reserved
LOCKED
Reserved
VSEL
Reserved
MDIV
Reserved
PDIV
Reserved
SDIV
EPLL_CON1
Reserved
K
The reset value of EPLL_CON and VPLL_CON generates 133 MHz and 54 MHz output clock respectively, if the
input clock frequency is 24 MHz.
Equation to calculate the output frequency:
FOUT = (MDIV+K/65536) X FIN / (PDIV X 2
where, MDIV, PDIV, SDIV for PLLs must meet the following conditions :
PDIV: 1 ≤ PDIV ≤ 63
MDIV: 16 ≤ MDIV ≤ 511
SDIV: 0 ≤ SDIV ≤ 5
K: 0 ≤ SDIV ≤ 65535
Fref (=FIN / PDIV): 4MHz ≤ Fref ≤ 30MHz
FVCO (=MDIV X FIN / PDIV):
330MHz ≤ FVCO ≤ 460MHz when VSEL=LOW.
Bit
[31] PLL enable control (0: disable, 1: enable)
[30] Reserved
[29] PLL locking indication
0 = Unlocked
1 = Locked
Read Only
[28] Reserved
[27] VCO frequency range selection
[26:25] Reserved
[24:16] PLL M divide value
[15:14] Reserved
[13:8] PLL P divide value
[7:3] Reserved
[2:0] PLL S divide value
Bit
[31:16] Reserved
PLL K value.
K value is used to fine-tune M divider value to meet
FOUT requirement exactly.
[15:0]
For this purpose, MDIV+K/65536 is used for M divider
value.
Also called as DSM (Delta-Sigma Modulator).
SDIV
)
Description
Description
3 CLOCK CONTROLLER
Initial State
0x0
0x0
0x0
0x0
0x1
0x0
0x85
0x0
0x3
0x0
0x2
Initial State
0x0
0x0
3-22