Samsung S5PC110 Manual page 415

S5PC110_UM
OTHERS
Reserved
ARM_PRESETn_TYPE
Reserved
CLKOUT
Reserved
CLEAR_DBGACK
SYSCON_INT_DISABLE
4.10.5.2 MISC Register (OM_STAT, R, Address = 0xE010_E100)
OM_STAT
Reserved
OM
Bit
1 = RELEASE_RET_UART_IO
For more information on list of PADs belonging to
UART I/O pad, refer to Section 4.2 PIN SUMMARY of
GPIO manual.
[27:18] Reserved
[17] ARM_PRESETn type selection
0 = Asserted when software reset is generated.
1 = Not asserted when software reset is generated.
[16:10] Reserved
[9:8] Control the XCLKOUT signal output. This bit is prior to
CLK_OUT register value. When this bit is '10' or '11',
XCLKOUT output selected clock is not only normal
mode but also Top block off status and sleep mode.
00 = Clock out signal from SYSCON
(by CLK_OUT SFR of CMU)
01 = Reserved
10 = XXTI (Main X-tal input)
11 = XUSBXTI (USB X-tal input)
[7:2] Reserved
[1] Clear DBGACK signal when this field has value 1.
Cortex-A8 asserts DBGACK signal to indicate the
system has entered DEBUG state. If DBGACK is
asserted, this state is stored in PMU until software
clears it using this field.
[0] Disables new interrupt to reach processor core.
Active HIGH.
Setting this field to HIGH is a mandatory step when
entering low-power mode.
This field is automatically cleared when low-power
mode entering sequence is completed.
Bit
[31:6] Reserved
[5:0] Operation mode value
Description
Description
4 POWER MANAGEMENT
Initial State
0x000
0
0x00
0x0
0x00
0
0
Initial State
0x000_0000
0x00
4-55