Cpu 2/7 (Clk, Misc, Jtag - Clevo W170HN Service Manual

Schematic Diagrams

CPU 2/7 (CLK, MISC, JTAG)

PU/PD for JTAG signals
1 . 05 V S _ V T T
3 . 3 V S
R 4 9 4
Sheet 3 of 49
CPU 2/7
(CLK, MISC, JTAG)
Buffered reset to CPU
1 2 , 2 2, 2 8 P L T _ R S T #
3 . 3 V
1 . 5 V S _ C P U
B
B - 4 CPU 2/7 (CLK, MISC, JTAG)
Sandy Bridge Processor 2/7 ( CLK,MISC,JTAG )
5 1_ 0 4 R 5 1 0 X D P _ T MS
5 1_ 0 4 R 5 0 6 X D P _ T D I _ R
* 5 1_ 0 4 R 5 0 8 X D P _ P R E Q #
X D P _ TD O_ R
5 1_ 0 4 R 5 1 1
5 1_ 0 4 R 5 1 3 X D P _T C LK
X D P _ TR S T #
5 1_ 0 4 R 5 0 5
H _ S N B _I V B #
2 3 H _ S N B _I V B #
1 K _ 04 XD P _ D B R _R
H _ C A T E R R #
R 4 9 7 *1 0 m i l _ s ho rt
2 3 , 3 4 H _ P E C I
R 10 9 5 6_ 1 % _0 4 H _ P R O C H OT # _ D
39 H _ P R O C H OT #
If PROCHOT# is not used, then it must be terminated
with a 56-O +-5% pull-up resistor to 1.05VS_VTT .
H _ T H R MT R I P #_ R
R 4 9 6 *1 0 m i l _ sh o rt
2 3 H _ T H R MT R I P #
R 4 9 5 *1 0 m i l _ sh o rt H _ P M_ S Y N C _ R
2 0 H _ P M _S Y N C
R 4 9 8 *1 0 m i l _ sh o rt H _ C P U P W R GD _R
2 3 H _ C P U P W R GD
P M S Y S _P W R G D _ B U F R 1 7 4 1 30 _ 1 %_ 0 4 V D D P W R G OO D _ R
1 . 0 5V S _V T T
B U F _ C P U _R S T #
3 . 3 V S
R 5 1 2
7 5_ 0 4
R 6 58
B U F _C P U _ R S T#
R 5 1 5
43 . 2 _ 1% _ 0 4
1 0K _0 4 D
Q 3 7B
5
G D MN 60 1 D W K -7
S
D
2
G Q3 7 A
S D M N 6 0 1D W K -7
3 4
R 5 2 4 R 5 18 * 1 . 5K _1 % _ 04
1 0 0K _0 4 C 6 21 R 5 17
6 8 p _5 0 V _ N P O _ 04
* 75 0 _ 1 %_ 0 4
3 . 3V
3 . 3 V
R 1 65 C 26 8 * 0. 1u _ 1 6V _ Y 5V _0 4
* 1 0K _0 4
R 16 6 U 11
1 . 5S _C P U _ P W R GD 3 8
* MC 74 V H C 1 G0 8 D F T1 G
1
* 10 K _ 0 4 Q 1 2
37 1 . 0 5 V S _ V TT _ P W R GD
4 D R A M P W R G D _ C P U
G 2
3 . 3V _E N _ D
* MT N 70 0 2 Z H S 3
Q 11
* 2N 3 90 4
U 4 9B
A 2 8
B C LK
C 2 6 A 2 7
P R OC _S E LE C T # B C L K #
A N 3 4
S K T O C C #
A 1 6
D P L L _ R E F _ S S C LK
A 1 5
D P L L _ R E F _ S S C L K #
A L3 3
C A TE R R #
A N 3 3 R 8
H _ P E C I _ R C P U D R A M R S T #
P E C I S M_ D R A MR S T #
A L3 2 A K 1 S M _ R C OMP _0
P R OC H O T# S M _ R C OM P [ 0 ]
A 5
S M _ R C OMP _1
S M _ R C OM P [ 1 ]
A 4 S M _ R C OMP _2
S M _ R C OM P [ 2 ]
A N 3 2
T H E R MT R I P #
A P 2 9
X D P _P R D Y #
P R D Y #
A P 2 7 X D P _P R E Q #
P R E Q #
A R 2 6 X D P _T C LK
T C K
A R 2 7 X D P _T M S
T MS
A M3 4 A P 3 0
X D P _T R S T#
P M _S Y N C TR S T #
A R 2 8
X D P _T D I _R
T D I
A P 2 6 X D P _T D O_ R
A P 3 3 T D O
U N C OR E P W R G OO D
A L 3 5 X D P _D B R _ R
V 8 D B R #
S M _D R A MP W R OK
A T 2 8 X D P _B P M0 _ R
B P M # [ 0 ]
A R 2 9 X D P _B P M1 _ R
B P M # [ 1 ]
A R 3 0 X D P _B P M2 _ R
B P M # [ 2 ]
A R 3 3 A T 3 0
X D P _B P M3 _ R
R E S E T # B P M # [ 3 ]
A P 3 2 X D P _B P M4 _ R
B P M # [ 4 ] A R 3 1
X D P _B P M5 _ R
B P M # [ 5 ]
A T 3 1 X D P _B P M6 _ R
B P M # [ 6 ] A R 3 2
X D P _B P M7 _ R
B P M # [ 7 ]
P Z 98 8 2 7-3 6 4 B -0 1F
H _ P R O C H OT #
Q1 6
G
H _ P R OC H O T# _ E C
MT N 70 0 2 Z H S 3 C 6 2 2
R 20 3 47 p _ 5 0V _ N P O_ 0 4
1 0 0K _0 4
R 2 00 *0 _ 0 4 CAD Not e: Ca paci tor need to b e pl aced
clo se t o buf fer outp ut pi n
1 . 5 V S _ C P U
R 15 7
*1 . 1 K _ 1 % _0 4
R 1 5 2 * 1 . 5K _ 1 % _ 04 V D D P W R G OO D _ R
R 15 8
*3 K _ 1 % _0 4
2 , 8 , 1 1 , 12 , 1 6 , 1 8, 19 , 2 0 , 22 , 2 3 , 2 4, 2 5 , 2 7 , 28 , 2 9 , 3 0, 3 3 , 3 5 , 37 , 3 8 , 3 9
6 , 9 , 1 0, 1 1 , 1 2 , 18 , 1 9 , 2 0, 2 1 , 2 2 , 23 , 2 4 , 2 5, 2 7 , 2 8, 29 , 3 0 , 31 , 3 2 , 3 3, 3 4 , 3 5 , 39
Processor Pullups/Pull downs
H _ P R O C H OT # 6 2_ 0 4
H _ C P U P W R G D _ R 1 0 K _ 0 4
TRAC E WI DTH 10MI L, LE NGTH <50 0MIL S
C L K _ E X P _ P 1 9
C L K _ E X P _ N 1 9
C L K _ D P _ P 1 9
DDR3 Compensation Signals
C L K _ D P _ N 1 9
S M _R C O MP _ 0 R 5 3 1
S M _R C O MP _ 1 R 5 2 8
S M _R C O MP _ 2 R 5 2 9
S3 circuit:- DRAM PWR GOOD logic
3 . 3 V 3 . 3 V
C 2 78
R 18 7 R 18 8
1 . 5 V S _ C P U
1
2 0 P M_ D R A M _P W R G D
4
2
3 8 1. 5S _ C P U _ P W R GD
U 1 4
*M C 7 4 V H C 1G 0 8D F T 1 G
R 1 8 6 0 _ 0 4
G
3 5 , 3 7, 38 S U S B
S3 circuit:- DRAM_RST# to memory
should be high during S3
1 . 5V
R 23 1 *0 _ 0 4
R 2 3 0
1 K _0 4
Q1 7
MT N 7 0 0 2 Z H S 3
C P U D R A MR S T # S D 1 K _ 04
R 2 3 5
R 2 2 5
D R A M R S T _ C N T R L 8 , 1 9
C 3 1 5
0 . 04 7 u _ 10 V _ X 7R _ 04
6 , 8, 9 , 1 0 , 2 5, 2 9 , 3 3 , 35 , 3 7 , 3 8 1 . 5 V
6 , 3 5 1 . 5 V S _ C P U
2 , 5 , 2 3 , 24 , 2 5 , 3 5, 3 9 1 . 0 5 V S _ V TT
3 . 3 V
3 . 3 V S
1 . 0 5 V S _ V T T
R 1 1 0
R 4 9 9
14 0 _ 1 %_ 0 4
25 . 5 _ 1 %_ 0 4
20 0 _ 1 %_ 0 4
R 17 5
2 0 0 _1 % _ 04
P MS Y S _ P W R G D _ B U F
R 16 8
* 39 _ 0 4
Q 13
* MT N 7 0 0 2Z H S 3
D D R 3_ D R A M R S T # 9 , 10