Cpu 2/7 (Clk, Misc, Jtag - Clevo B5130M Service Manual

CPU 2/7 (CLK, MISC, JTAG)

Processor Compensation
PROCESSOR
Signals
R 4 1 9 4 9 . 9_ 1 % _ 04 H _ C O MP 0
R 4 3 3 4 9 . 9_ 1 % _ 04 H _ C O MP 1
TR ACE WIDT H 10 MIL, LEN GTH <500 MILS
R 4 2 1 2 0 _1 % _ 04 H _ C O MP 2
R 4 2 4 2 0 _1 % _ 04 H _ C O MP 3
Processor Pullups 2 4 , 3 6
1 . 1 V S _ V T T
R 1 10
4 3 H _ P R O C H OT #
If PRO CHOT # is not use d, t hen it mu st b e te rmin ated
R 1 2 5 4 9 . 9_ 1 % _ 04 H _ C A T E R R #
wi th a 50- O pu ll-u p re sist or t o VTT _1.1 rai l.
2 4 H _ T H R MT R I P #
R 1 0 9 6 8 _0 4 H _ P R O C H OT # _D
R 1 0 7 * 68 _ 0 4 H _ C P U R S T #
2 1 H _ P M_ S Y N C
S Y S _ A G E N T _ P W R OK
R 1 1 5
2 1 , 43 D E L A Y _ P W R GD
C 1 1 26
R 1 1 4
0. 1 u _ 10 V _ X 5 R _ 04
24 H _ C P U P W R G D
X 7R -> X 5R C 990 70 3 R 1 5 6
2 1 P M_ D R A M_ P W R GD
2 1 H _ V T T P W R G D
Con nect to the Proce ssor (VT TPWR GOOD ) VT T_1. 1 VR pow er
goo d si gnal to proce ssor . Si gnal vol tage lev el i s 1. 1 V.
R 1 5 9
2 3 , 2 8, 3 1 , 3 2, 36 B U F _ P LT _ R S T #
Si gnal fro m PC H to Pro cesso r
Co nnec t to PCH (PL T_RS T#)
(n eeds to be l evel tra nslat ed
fr om 3 .3 V to 1.1 V).
+1 . 5 S _ C P U
D R A MP W R G D _ C P U
R 13 4 R 1 5 7
1 . 1 K _ 1% _ 0 4 *1 . 5 K _ 1% _ 0 4
V D D P W R G OO D _ R
R 15 8
3 K _ 1% _ 0 4
2/7 ( CLK,MISC,JTAG )
U 4 0 B
H _ C O MP 3 A T 2 3
C OM P 3
H _ C O MP 2 A T 2 4
C OM P 2
H _ C O MP 1 G 1 6
C OM P 1
H _ C O MP 0 A T 2 6
C OM P 0
A H 2 4
S K TO C C #
H _ C A TE R R # A K 1 4
C A T E R R #
A T 1 5
R 12 1 0_ 0 4
H _ P E C I
P E C I
H _ P R OC H OT # _ D A N 2 6
0 _ 04
P R OC H O T #
A K 1 5
T H E R M TR I P #
H _ C P U R S T# A P 2 6
R E S E T _ OB S #
A L 1 5
P M_ S Y N C
S Y S _ A G E N T _ P W R OK A N 1 4
* 0 _0 4
V C C P W R G OO D _ 1
*1 0 m i l _ s ho rt
A N 2 7
V C C P W R G OO D _ 0
V D D P W R GOO D _ R A K 1 3
*1 0 m i l _ s ho rt
S M_ D R A MP W R OK
A M 1 5
V TT P W R GO OD
H _ P W R GD _X D P A M 2 6
T A P P W R G OO D
1 . 5 K _ 1 %_ 0 4 P L T_ R S T# _ R A L 1 4
R S T I N #
R 15 5
7 5 0_ 1 % _0 4 P Z 9 89 2 7 -3 64 1 -0 1F
1. 5 V
R 24 6
* 1K _0 4
R 2 5 0 0 _0 4
D D R 3 _ D R A MR S T # D S
1 0 , 1 1 D D R 3 _D R A M R S T#
Q3 2
*M TN 7 00 2 Z H S 3
R 23 4 *0 _ 04
2 4 D R A MR S T _C N T R L_ P C H
9 D R A MR S T _C N T R L
C 3 60
*4 7 0p _ 5 0V _X 7 R _ 0 4
DDR3 Compensation Signals
A 16
B C L K _ C P U _ P 2 4
B C L K
B 16 S M_ R C OM P _ 0
B C LK # B C L K _ C P U _ N 2 4
A R 3 0 S M_ R C OM P _ 1
B C L K _I T P
A T3 0
B C L K _ I TP #
S M_ R C OM P _ 2
E 16
C L K _ E X P _ P 2 0
P E G_ C L K
D 1 6
C L K _ E X P _ N 2 0
P E G_ C LK #
A 18
C L K _ D P _ P 2 0
D P L L _R E F _ S S C L K A 17
C L K _ D P _ N 20
D P L L _ R E F _ S S C LK #
F 6
C P U _ D R A M R S T #
S M_ D R A MR S T #
1 . 1 V S _ V T T
A L1
S M_ R C OM P _ 0
S M _ R C O MP [ 0 ]
A M1 S M_ R C OM P _ 1
R 1 3 0 1 0 K _ 0 4
S M _ R C O MP [ 1 ] A N 1
S M_ R C OM P _ 2 R 1 3 1 1 0 K _ 0 4
S M _ R C O MP [ 2 ]
A N 1 5 P M_ E X T TS #[ 0 ] R 1 5 3 * 0 _0 4
P M _E XT _ T S #[ 0 ]
A P 15 P M_ E X T TS #[ 1 ]
R 1 2 9 * 0 _0 4
P M _E XT _ T S #[ 1 ]
R 1 2 8 * 1 2. 4 K _ 1 % _0 4
A T2 8
P R D Y #
A P 27 X D P _ P R E Q#
P R E Q #
A N 2 8
X D P _ T C L K
T C K
A P 28 X D P _ T MS
T MS A T2 7
X D P _ T R S T # X D P _ T MS R 6 8
T R S T #
X D P _ T D O _ M R 4 1 8
A T2 9
X D P _ T D I _ R X D P _ T D I _ R R 6 7
T D I
A R 2 7 X D P _ P R E Q# R 6 9
TD O A R 2 9
X D P _ T D I _ M
T D I _ M
A P 29 X D P _ T D O _M
T D O_ M
A N 2 5 X D P _ T C L K
R 6 0
D B R #
X D P _ T R S T # R 1 0 8
A J2 2
B P M #[ 0 ]
A K 22
B P M #[ 1 ] A K 24
B P M #[ 2 ]
A J2 4
B P M #[ 3 ] A J2 5
XD P _ TD O_ M R 4 16 * 1 0m i l _s h o rt
B P M #[ 4 ]
A H 2 2
B P M #[ 5 ]
A K 23
B P M #[ 6 ]
A H 2 3
B P M #[ 7 ]
2 1 , 41 1 . 1 V S _ V T T_ P W R GD
3 . 3 V
3. 3 V
R 1 6 3
*1 0 K _ 04
R 16 2
* 10 K _ 0 4 Q1 3
+ 1 . 5S _C P U
G
*M TN 7 00 2 Z H S 3
B
Q 12
* 2N 3 90 4
C P U _ D R A MR S T #
1 . 1 V S _ V T T 2, 6 , 7 , 1 9 , 20 , 2 1 , 2 4, 2 5 , 2 6, 3 9 , 4 1 , 42 , 4 3
R 2 41
+ 1 . 5 S _ C P U 7, 3 7
1 . 5 V 1 0 , 1 1, 31 , 3 7 , 40
* 1 00 K _ 0 4
3 . 3 V 3 , 1 2 , 1 3, 1 7 , 1 9, 2 0 , 2 1 , 23 , 2 4 , 26 , 2 8 , 2 9, 3 1 , 3 2 , 33 , 3 4 , 37 , 3 9 , 4 0, 4 1 , 4 4
Schematic Diagrams
R 4 4 1 10 0 _ 1% _ 0 4
R 4 4 0 24 . 9 _ 1% _ 0 4
R 4 3 9 13 0 _ 1% _ 0 4
P M_ E X TT S # _ E C 3
T S # _ D I M M0 _ 1 10 , 1 1
Sheet 4 of 53
1 . 1 V S _ V T T
* 5 1_ 0 4
5 1 _ 04 CPU 2/7
* 5 1_ 0 4
* 5 1_ 0 4
(CLK, MISC, JTAG)
* 5 1_ 0 4
5 1 _ 04
X D P _T D I _M
3 . 3 V
C 2 22 *. 1 u _1 0 V _ X7 R _0 4
U 1 1
*7 4A H C 1 G 08 G W
1
4 D R A M P W R G D _ C P U
2
+ 1 . 5 S _C P U _ P W R GD 4 0
CPU 2/7 (CLK, MISC, JTAG) B - 5