Cpu 7/7 (Reserved) - Clevo W170HN Service Manual

CPU 7/7 (RESERVED)

CFG Straps for Processor
PEG St atic L ane Re versal - CFG2 is fo r the 16x
CFG2 1:(De fault) Norma l Oper ation; Lane #
defin ition matche s sock et pin map de finiti on
0:Lan e Reve rsed
C F G2 R 5 0 3 * 1 K _0 4
Displa y Port Prese nce St rap
1:(De fault) Disab led; N o Physi cal Di splay Port
CFG4
attac hed to Embed ded Di splay P ort
0:Ena bled; An ext ernal Display Port device is
conne cted t o the Embedd ed Disp lay Po rt
C F G4 R 4 9 3 * 1 K _0 4
PC IE Port Bifur cation Strap s
11: (D efault ) x16 - Devic e 1 fu nction s 1 an d 2 di sabled
10: x8 , x8 - Devic e 1 fun ction 1 enab led ; functi on 2 di sabled
CFG[6:5]
01: Re served - (De vice 1 functi on 1 d isable d ; fu nction 2 enab led)
00: x8 ,x4,x4 - Dev ice 1 f unctio ns 1 a nd 2 e nabled
C F G 5
R 49 2 *1 K _ 0 4
C F G 6 R 50 0 *1 K _ 0 4
R 5 14
3 . 3 V
H _ S N B _I V B #_ P W R C TR L
PEG D EFER T RAINING
1: ( Defaul t) PEG Train immedi ately follow ing xxR ESETB de ass ertion
CFG7
0: P EG Wai t for B IOS fo r trai ning
C F G7 R 4 9 1 * 1K _0 4
Sandy Bridge Processor 7/7 ( RESERVED )
U 4 9 E
A K 2 8
C F G0
C F G [ 0 ]
A K 2 9
C F G [ 1 ]
C F G2 A L 2 6
C F G [ 2 ]
A L 2 7
C F G [ 3 ]
C F G4 A K 2 6
C F G [ 4 ]
A L 2 9
C F G5
C F G [ 5 ]
C F G6 A L 3 0
A M 3 1 C F G [ 6 ]
C F G7
C F G [ 7 ]
A M 3 2
A M 3 0 C F G [ 8 ]
C F G [ 9 ]
A M 2 8
C F G [ 1 0]
A M 2 6
C F G [ 1 1]
A N 2 8
C F G [ 1 2]
A N 3 1
C F G [ 1 3]
A N 2 6
C F G [ 1 4]
A M 2 7
A K 3 1 C F G [ 1 5]
C F G [ 1 6]
A N 2 9
C F G [ 1 7]
H _ C P U _ R S V D 1 A J 3 1
V A X G_ V A L _ S E N S E
A H 3 1
H _ C P U _ R S V D 2
V S S A X G_ V A L_ S E N S E
H _ C P U _ R S V D 3 A J 3 3
A H 3 3 V C C _ V A L _S E N S E
H _ C P U _ R S V D 4
V S S _ V A L _ S E N S E
A J 2 6
R S V D 5
B 4
V R E F _C H _ A _ D I MM
R S V D 6
V R E F _C H _ B _ D I MM D 1
R S V D 7
F 2 5
R S V D 8
F 2 4
R S V D 9
F 2 3
R S V D 1 0
D 2 4
R S V D 1 1
G 2 5
R S V D 1 2
G 2 4
E 2 3 R S V D 1 3
R S V D 1 4
D 2 3
C 3 0 R S V D 1 5
R S V D 1 6
A 3 1
R S V D 1 7
B 3 0
R S V D 1 8
B 2 9
R S V D 1 9
D 3 0
R S V D 2 0
B 3 1
R S V D 2 1
A 3 0
C 2 9 R S V D 2 2
R S V D 2 3
J 2 0
1 0K _ 1 % _ 04
R S V D 2 4
B 1 8
R S V D 2 5
H _ S N B _ I V B # _ P W R C T R L _ R A 1 9
R 5 1 6 *1 0 m i l _ s ho rt
V C C I O_ S E L
J 1 5
R S V D 2 7
On CR B
H_SNB _IVB#_P WRCTRL = low , 1.0V
H_SNB _IVB#_P WRCTRL = hig h/NC, 1.05V
P Z 9 8 8 27 -3 6 4B -01 F
2 , 3 , 1 1 , 1 2, 1 6 , 1 8 , 19 , 2 0 , 2 2, 2 3 , 2 4 , 25 , 2 7 , 2 8, 29 , 3 0 , 3 3, 3 5 , 3 7 , 38 , 3 9
1 . 5V
R 6 4 2 *0 _ 0 4
R 1 5 5
10 /21
Q9 1K _ 1 % _ 04
L 7
*A O 3 40 2 L
R S V D 2 8
A G 7 V R E F _ C H _A _D I MM S D MV R E F _ D Q _D I M 0
R 2 5 4
R S V D 2 9 A E 7
R S V D 3 0
A K 2
R S V D 3 1
W 8 R 14 9 R 1 5 0 C 3 5 7
R S V D 3 2
* 1K _0 4
1K _ 1 % _ 04
A T 2 6
R S V D 3 3
A M 33
R S V D 3 4 A J 2 7
R S V D 3 5
D R A MR S T _C N T R L 3, 1 9
1 . 5 V
T 8
R S V D 3 7
J 1 6
R 6 4 3 *0 _ 0 4
R S V D 3 8
H 16
R S V D 3 9 G 16
R S V D 4 0
R 1 5 9 10/21
Q1 0
*A O 3 40 2 L 1 K _ 1% _ 0 4
V R E F _ C H _B _D I MM S D MV R E F _ D Q _ D I M 1 R 2 7 7
A R 35
R S V D 4 1
A T 3 4
R S V D 4 2
A T 3 3
R 15 3 R 1 6 0 C 3 67
R S V D 4 3
A P 3 5 * 1K _0 4
R S V D 4 4 A R 34
1 K _ 1% _ 0 4
R S V D 4 5
B 3 4
R S V D 4 6 D R A M R S T _ C N T R L 3 , 1 9
A 3 3
R S V D 4 7
A 3 4
R S V D 4 8 B 3 5
R S V D 4 9
C 35
R S V D 5 0
A J 3 2
R S V D 5 1
A K 3 2
R S V D 5 2
A H 27
V C C _D I E _ S E N S E
A N 35
R S V D 5 4
A M 35
R S V D 5 5
A T 2
R S V D 5 6
A T 1
R S V D 5 7
A R 1
R S V D 5 8
B 1
K E Y
3 , 6 , 9, 10 , 2 5 , 2 9, 3 3 , 3 5 , 37 , 3 8 1 . 5V
3 . 3V
Schematic Diagrams
0 _ 04
MV R E F _ D Q _D I MM A 9
Sheet 8 of 49
CPU 7/7
0 _ 04
MV R E F _ D Q_ D I M MB 10
(RESERVED)
CPU 7/7 (RESERVED) B - 9