Cpu 2/7 (Clk, Misc - Clevo S3100 Service Manual

CPU 2/7 (CLK, MISC)

PROCESSOR
Processor Compensation
Signals
R137 49.9_1%_04 H_COMP0
H_COMP1
R138 49.9_1%_04
R26 20_1%_04 H_COMP2
R27 20_1%_04 H_COMP3
TRACE WIDTH 10MIL, LENGTH <500MILS
Processor Pullups
1.1VS_VTT
R145 49.9_1%_04 H_CATERR#
H_PROCHOT#_D
R17 68_04
H_CPURST#
R18 *68_04
19,27 H_PECI
If PROCHOT# is not used, then it must be terminated
with a 50-O pull-up resistor to VTT_1.1 rail.
19 H_THRMTRIP#
16 H_PM_SY NC
R223 *0_04
16,36 DELAY_PWRGD
R222 *10mil_short
19 H_CPUPWRGD
R182 *10mil_short
16 PM_DRAM_PWRGD
16 H_VTTPWRGD
Connect to the Processor (VTTPWRGOOD) VTT_1.1 VR power
good signal to processor. Signal voltage level is 1.1 V.
R191
18,23,25,27 BUF_PLT_RST#
Signal from PCH to Processor
Connect to PCH (PLT_RST#)
(needs to be level translated
from 3.3 V to 1.1 V).
20100127 D02
1.5V_CPU
3.3V
R184
1.1K_1%_04 R219
VDDPWRGOOD_R
U16
1
R221 R220 *1.5K_1%_04 DRAMPWRGD_CPU 4
2
3K_1%_04
*MC74VHC1G08DFT1G
Intel change
4.75K -->1.1K
12K -->3K
2/7 ( CLK,MISC,JTAG )
DDR3 Compensation Signals
SM_RCOMP_0
R161
SM_RCOMP_1
R163
SM_RCOMP_2 R162
U4B
H_COMP3 AD71
COMP3
H_COMP2 AC70
COMP2
H_COMP1 AD69
COMP1
BCLK_ITP#
AE66
H_COMP0
COMP0
PEG_CLK#
PROC_DETECT M71
PROC_DETECT
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
H_CATERR# N61
CATERR#
N19 SM_DRAMRST#
PECI
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
H_PROCHOT#_D N67
PROCHOT#
PM_EXT_TS#[0]
PM_EXT_TS#[1]
N17
THERMTRIP#
H_CPURST# N70
RESET_OBS#
M17
PM_SY NC
SY S_AGENT_PWROK AM7
VCCPWRGOOD_1
Y 67
VCCPWRGOOD_0
AM5
VDDPWRGOOD_R
SM_DRAMPWROK
H15
VTTPWRGOOD
H_PWRGD_XDP Y 70
TAPPWRGOOD
G3
1.5K_1%_04 PLT_RST#_R
RSTIN#
R190
750_1%_04
IC,ARD_BGA,R1P0
*8.2K_04
IN3.3V
1.1VS_VTT_PWRGD 16,32,34
R180 0_04
BSS138 ( VGS 1.5V )
100_1%_04 Q8
* RJU003N03T106
SM_DRAMRST# S D
24.9_1%_04
130_1%_04
R217
*100K_04
C324
*47n_50V_04
AK7
BCLK_CPU_P 19
BCLK
AK8
BCLK_CPU_N 19
BCLK#
K71 BCLK_ITP
BCLK_ITP
J70
BCLK_ITP#
L21
CLK_EXP_P 15
PEG_CLK J21
CLK_EXP_N 15
Y2
CLK_DP_P 15
W4
CLK_DP_N 15
BJ12
SM_DRAMRST#
1.1VS_VTT
BV33 SM_RCOMP_0
BP39
SM_RCOMP_1
R133 10K_04
BV40 SM_RCOMP_2 R135 10K_04
AV66 PM_EXTTS#[0]
R136 * 0_04
AV64 PM_EXTTS#[1]
R134 * 0_04
R131 * 12. 4K_1%_04
U71 PRDY #
PRDY#
U69 XDP_PREQ#
PREQ#
T67 XDP_TCLK
TCK
N65 XDP_TMS XDP_TDO_R
R140 *51_04
TMS
P69
XDP_TRST#
TRST#
T69
XDP_TDI_R
TDI T71
XDP_TDO_R
TDO
P71 XDP_TDI_M
TDI_M
T70 XDP_TDO_M
TDO_M
XDP_TMS
R142 *51_04
W71 DBR# XDP_TDO_M
R20 51_04
DBR#
XDP_TDI_R R25 *51_04
XDP_PREQ# R21 *51_04
J69
XDP_TDO_R R139 51_04
BPM#[0] J67
BPM#[1]
J62
BPM#[2]
K65
BPM#[3]
K62
BPM#[4]
J64
BPM#[5]
K69 XDP_TCLK
R141 *51_04
BPM#[6]
M69 XDP_TRST#
R143 51_04
BPM#[7]
DBR#
R195 1K_04
XDP_TDO_M R19 *10mil_short
3.3VS 2,10,11,12,13,14,15,16,17,18,19,20,21,23,24,25,26,27,28,29,30,31,35,36
3.3V 3,12,14,15,16,18,19,20,21,23,24,25,28,31,32,34,35,36
1.5V 9,10,11,21,23,30,31,32
1.5V_CPU 6,7,31
1.1VS_VTT 2,6,7, 14,15,16,19,20,21,34,35,36
Schematic Diagrams
1.5V
R218
*1K_04
DDR3_DRAMRST# 10,11
DRAMRST_CTRL 9,19
? ? IBEX CONTROL
Sheet 4 of 43
CPU 2/7
(CLK, MISC)
PM_EXTTS#_EC 3
TS#_DIMM0_1 10,11
1.1VS_VTT
3.3VS
XDP_TDI_M
CPU 2/7 (CLK, MISC) B - 5