Cpu 2/7 (Clk, Misc, Jtag - Clevo B5100M Service Manual

CPU 2/7 (CLK, MISC, JTAG)

Processor Compensation
PROCESSOR 2/7
Signals
H_COMP0
R419 49.9_1%_04
R433 49.9_1%_04 H_COMP1
TRACE WIDTH 10MIL, LENGTH <500MILS
R421 20_1%_04 H_COMP2
R424 20_1%_04 H_COMP3
Processor Pullups
24,36 H_PECI
1.1VS_VTT
R110
43 H_PROCHOT#
If PROCHOT# is not used, then it must be terminated
R125 49.9_1%_04 H_CATERR#
with a 50-O pull-up resistor to VTT_1.1 rail.
24 H_THRMTRIP#
R109 68_04 H_PROCHOT#_D
H_CPURST#
R107 *68_04
21 H_PM_SYNC
SYS_AGENT_PWROK
R115 *0_04
21,43 DELAY _PWRGD
C1126 R114 *10mil_short
0.1u_10V_X7R_04
24 H_CPUPWRGD
R156 *10mil_short
21 PM_DRAM_PWRGD
21 H_VTTPWRGD
Connect to the Processor (VTTPWRGOOD) VTT_1.1 VR power
good signal to processor. Signal voltage level is 1.1 V.
R159 1.5K_1%_04
23,28,31,32,36 BUF_PLT_RST#
Signal from PCH to Processor
Connect to PCH (PLT_RST#)
(needs to be level translated
from 3.3 V to 1.1 V).
+1.5S_CPU
DRAMPWRGD_CPU
R134 R157
1.1K_1%_04 *1.5K_1%_04
VDDPWRGOOD_R
R158
3K_1%_04
10,11
24
( CLK,MISC,JTAG )
U40B
H_COMP3 AT23
COMP3
AT24 BCLK
H_COMP2
COMP2 BCLK#
H_COMP1 G16
COMP1 BCLK_ITP
BCLK_ITP#
H_COMP0 AT26
COMP0
PEG_CLK
PEG_CLK#
AH24
SKTOCC#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
H_CATERR# AK14
CATERR#
SM_DRAMRST#
AT15
R121 0_04
PECI
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
H_PROCHOT#_D AN26
0_04
PROCHOT#
PM_EXT_TS#[0]
PM_EXT_TS#[1]
AK15
THERMTRIP#
PRDY#
PREQ#
TCK
H_CPURST# AP26
RESET_OBS# TMS
TRST#
AL15
PM_SYNC TDI
TDO
TDI_M
SYS_AGENT_PWROK AN14
VCCPWRGOOD_1 TDO_M
AN27 DBR#
VCCPWRGOOD_0
BPM#[0]
VDDPWRGOOD_R AK13
SM_DRAMPWROK BPM#[1]
BPM#[2]
AM15 BPM#[3]
VTTPWRGOOD BPM#[4]
BPM#[5]
BPM#[6]
H_PWRGD_XDP AM26
TAPPWRGOOD BPM#[7]
AL14
PLT_RST#_R
RSTIN#
R155
750_1%_04 PZ98927-3641-01F
1.5V
R246
*1K_04
R250 0_04
DDR3_DRAMRST# D S
CPU_DRAMRST#
DDR3_DRAMRST#
Q32
*MTN7002ZHS3
R241
R234 *0_04 *100K_04
DRAMRST_CNTRL_PCH
9 DRAMRST_CNTRL
C360
*470p_50V_X7R_04
DDR3 Compensation Signals
A16
BCLK_CPU_P 24
B16
SM_RCOMP_0 R441 100_1%_04
BCLK_CPU_N 24
AR30 SM_RCOMP_1
R440 24.9_1%_04
AT30
SM_RCOMP_2 R439 130_1%_04
E16
CLK_EXP_P 20
D16
CLK_EXP_N 20
A18
CLK_DP_P 20
A17
CLK_DP_N 20
F6 CPU_DRAMRST#
1.1VS_VTT
AL1 SM_RCOMP_0
AM1
SM_RCOMP_1 R130 10K_04
AN1
SM_RCOMP_2 R131 10K_04
AN15 PM_EXTTS#[0]
R153 *0_04
PM_EXTTS#_EC 3
AP15 PM_EXTTS#[1] R129 *0_04
TS#_DIMM0_1 10,11
R128 *12.4K_1%_04
AT28
AP27 XDP_PREQ#
AN28 1.1VS_VTT
XDP_TCLK
AP28 XDP_TMS
AT27 XDP_TRST# XDP_TMS
R68 *51_04
XDP_TDO_M R418 51_04
AT29 XDP_TDI_R XDP_TDI_R R67 *51_04
AR27
XDP_PREQ# R69 *51_04
AR29
XDP_TDI_M
AP29 XDP_TDO_M
AN25 XDP_TCLK R60 *51_04
XDP_TRST# R108 51_04
AJ22
AK22
AK24
AJ24
AJ25
XDP_TDO_M R416 *10mil_short XDP_TDI_M
AH22
AK23
AH23
3.3V
C222 *.1u_10V_X7R_04
U11
*74AHC1G08GW
1
21,41 1.1VS_VTT_PWRGD
4
DRAMPWRGD_CPU
2
3.3V
3.3V
R163
*10K_04
R162
+1.5S_CPU_PWRGD 40
*10K_04 Q13
+1.5S_CPU
G
*MTN7002ZHS3
B Q12
*2N3904
1.1VS_VTT 2,6,7,19,20,21,24,25,26,39,41,42,43
+1.5S_CPU 7,37
1.5V 10,11,31,37,40
3.3V 3,12,13,17,19,20,21,23,24,26,28,29,31,32,33,34,37,39,40,41,44
CPU 2/7 (CLK, MISC, JTAG) B - 5
Schematic Diagrams
Sheet 4 of 53
CPU 2/7
(CLK, MISC, JTAG)