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Schematic Diagrams
PROCESSOR/ CLK, MISC, JTAG
PU/PD for JTAG signals
1. 0 5 V S _ V T T
3. 3V S
Sheet 3 of 46
PROCESSOR/ CLK,
MISC, JTAG
1 7 , 23
P L T _ R S T #
B - 4 PROCESSOR/ CLK, MISC, JTAG
Sandy Bridge Processor 2/7
5 1 _ 04
R 4 1 6
X D P _T M S
X D P _T D I _R
5 1 _ 04
R 1 0 8
*5 1 _ 04
R 1 0 9
X D P _P R E Q #
X D P _T D O_ R
5 1 _ 04
R 4 1 5
5 1 _ 04
R 4 1 4
X D P _T C LK
X D P _T R S T #
5 1 _ 04
R 9 5
H _ S N B _ I V B #
1 8
H _ S N B _ I V B #
XD P _ D B R _ R
R 40 7
1 K _ 0 4
H _ C A TE R R #
H _ P E C I _ R
R 41 1
* 10 m i l _ 0 4
18 , 2 8
H _P E C I
R 40 5
5 6_ 1 % _0 4
H _ P R O C H OT # _D
37
H _ P R O C H OT #
If P ROC HO T# i s n ot u se d, th en i t mu st
be t erm in at ed wi th a 6 8- O + -5 % pu ll -up
re si sto r to 1 .05 VS _V TT .
R 41 7
* 10 m i l _ 0 4
H _ TH R M T R I P # _ R
1 8
H _ T H R MT R I P #
R 41 9
* 10 m i l _ 0 4
P M_ S Y N C _ R
15
H _ P M_ S Y N C
R 41 8
* 10 m i l _ 0 4
H _ C P U P W R G D _ R
18
H _C P U P W R G D
P MS Y S _ P W R GD _ B U F
R 6 0
1 30 _ 1 %_ 0 4
V D D P W R GOO D _ R
Buffered reset to CPU
1 . 0 5 V S _ V TT
B U F _C P U _ R S T#
R 1 0 5
7 5 _1 % _ 0 4
R 1 0 4
11/0 4
43 _ 1 % _0 4
6
D
3 . 3V S
Q3 6 A
R 5 3 0
10 K _ 0 4
2
G
MT D N 7 00 2 Z H S 6 R
S
3
1
D
5
G
Q3 6 B
S
MT D N 7 00 2 Z H S 6 R
4
R 1 1 2
*1 . 5 K _1 % _ 04
R 5 3 1
C 9 6
2 8
H _ P R O C H OT _ E C
R 1 0 6
10/1
* 75 0 _ 1% _ 0 4
CAD Note : Ca paci tor need to be p lace d
clos e to buf fer outp ut p in
( CLK,MISC,JTAG )
U 3 4B
A 2 8
B C L K
C 2 6
A 2 7
P R OC _S E L E C T #
B C L K #
A N 3 4
S K T OC C #
A 1 6
D P L L _ R E F _ S S C L K
A 1 5
D P LL _ R E F _S S C L K #
A L3 3
C A TE R R #
A N 3 3
R 8
C P U D R A M R S T #
P E C I
S M_ D R A M R S T #
A L3 2
A K 1
S M _R C O MP _ 0
P R OC H OT #
S M_ R C OM P [ 0 ]
A 5
S M _R C O MP _ 1
S M_ R C OM P [ 1 ]
A 4
S M _R C O MP _ 2
S M_ R C OM P [ 2 ]
A N 3 2
T H E R MT R I P #
A P 2 9
X D P _ P R D Y #
P R D Y #
A P 2 7
X D P _ P R E Q#
P R E Q #
A R 2 6
X D P _ T C L K
T C K
A R 2 7
X D P _ T MS
A M3 4
T M S
A P 3 0
X D P _ T R S T #
P M _S Y N C
T R S T #
A R 2 8
X D P _ T D I _ R
T D I
A P 2 6
X D P _ T D O _ R
A P 3 3
T D O
U N C O R E P W R G OOD
A L 35
X D P _ D B R _ R
V 8
D B R #
S M _D R A M P W R OK
A T 28
X D P _ B P M 0 _R
B P M# [ 0 ]
A R 2 9
X D P _ B P M 1 _R
B P M# [ 1 ]
A R 3 0
X D P _ B P M 2 _R
B P M# [ 2 ]
A R 3 3
A T 30
X D P _ B P M 3 _R
R E S E T #
B P M# [ 3 ]
A P 3 2
X D P _ B P M 4 _R
B P M# [ 4 ]
A R 3 1
X D P _ B P M 5 _R
B P M# [ 5 ]
A T 31
X D P _ B P M 6 _R
B P M# [ 6 ]
A R 3 2
X D P _ B P M 7 _R
B P M# [ 7 ]
P Z 9 8 82 7 -3 64 B -0 1 F
1 0/ 29
H _P R OC H O T#
Q 1 4
C 5 15
G
M T N 7 00 2 Z H S 3
R 9 1
1 0 0 K _0 4
R 9 0
*0 _ 04
2 , 5 , 1 8 , 19 , 2 0 , 3 5, 3 7
6, 8 , 9 , 1 0 , 20 , 2 7 , 3 2, 3 4
2, 8 , 1 1 , 13 , 1 5 , 1 7, 1 9 , 2 0, 2 2 , 2 3, 27 , 2 9 , 31 , 3 2 , 3 4, 3 6
9 , 1 0 , 1 1, 1 2 , 1 3, 1 4 , 1 5 , 16 , 1 7 , 18 , 1 9 , 2 0, 2 3 , 2 4, 2 5 , 2 6, 28 , 2 9 , 30 , 3 1 , 3 2, 3 7
Processor Pullups/Pull downs
1. 0 5 V S _ V T T
H _P R OC H O T#
6 2 _ 04
R 4 1 0
H _ C P U P W R GD _ R
1 0 K _ 0 4
R 4 1 2
*0 . 1 u _1 0 V _ X 7R _0 4
C 5 85
11/03
TR AC E WI DTH 1 0M IL , LEN GT H <5 00 MIL S
C L K _ E X P _P
14
C L K _ E X P _N
1 4
DDR3 Compensation Signals
S M_ R C OM P _ 0
R 4 1 3
14 0 _ 1% _ 0 4
C L K _ D P _ P 1 4
S M_ R C OM P _ 1
R 3 8 2
25 . 5 _ 1% _ 0 4
C L K _ D P _ N
14
S M_ R C OM P _ 2
R 3 8 1
20 0 _ 1% _ 0 4
S3 circuit:- DRAM PWR GOOD logic
3 . 3V
1 . 5V S _C P U
123 0 D02
R 7 3
R 5 7
* 2 00 _ 1 %_ 0 4
1 0 K _0 4
D 2 0
1
A
1 5
P M_ D R A M_ P W R GD
3
C
P M S Y S _P W R GD _ B U F
2
A
1 5, 3 4
1 . 8 V S _ P W R G D
*B A T 5 4 A W GH
R 58
* 39 _ 0 4
R 5 9
0 _ 0 4
Q1 0
G
3 2, 3 4 , 3 5
S U S B
*M T N 7 0 02 Z H S 3
S3 circuit:- DRAM_RST# to memory
should be high during S3
1 . 5V
R 4 7
*0 _ 0 4
R 4 5
1K _ 0 4
Q8
MT N 70 0 2 Z H S 3
C P U D R A M R S T #
S
D
1 K _ 0 4
D D R 3 _ D R A MR S T # 9 , 1 0
R 4 8
R 4 6
D R A MR S T _C N T R L 8 , 1 4
C 2 2
0 . 0 47 u _ 10 V _ X 7R _ 04
1 . 05 V S _ V T T
6, 3 2
1 . 5V S _C P U
1 . 5V
3 . 3V
3 . 3V S
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