Cpu 2/7 (Clk, Misc, Jtag - Clevo B7130 Service Manual

CPU 2/7 (CLK, MISC, JTAG)

Processor Compensation
PROCESSOR 2/7
Signals
R 4 1 9 4 9 . 9 _1 % _ 04 H _ C O MP 0
R 4 3 3 4 9 . 9 _1 % _ 04 H _ C O MP 1
TRA CE W IDTH 10M IL, LENG TH < 500M ILS
H _ C O MP 2
R 4 2 1 2 0 _ 1% _ 0 4
R 4 2 4 2 0 _ 1% _ 0 4 H _ C O MP 3
Processor Pullups
24 ,3 6
1.1 V S _ V T T
R 1 1 0
4 3 H _ P R O C H OT #
If PROC HOT# is not used , th en it mus t be ter mina ted
R 1 2 5 4 9 . 9 _1 % _ 04 H _ C A T E R R #
wit h a 50-O pul l-up res isto r to VTT_ 1.1 rail .
24 H _T H R M TR IP #
R 1 0 9 6 8 _ 04 H _ P R O C H OT # _D
R 1 0 7 * 68 _ 0 4 H _ C P U R S T #
21 H _ P M _S Y N C
S Y S _A GE N T_ P W R OK
R 11 5
2 1 , 4 3 D E L A Y _ P W R GD
C 1 1 26
R 11 4
0. 1u _ 1 0V _ X 5 R _ 0 4
2 4 H _ C P U P W R GD
X 7R - > X 5R C 99 07 03 R 15 6
2 1 P M_ D R A M_ P W R GD
2 1 H _V T T P W R GD
Conn ect to t he P roce ssor (VTT PWRG OOD) VTT _1.1 VR powe r
good sig nal to p roce ssor. Sig nal volt age leve l is 1.1 V.
R 15 9
2 3 , 2 8 , 31 ,3 2 , 36 B U F _ P L T_ R S T#
Sig nal from PCH to Proce ssor
Con nect to PCH (PLT _RST# )
(ne eds to b e le vel trans late d
fro m 3. 3 V to 1 .1 V ).
+ 1.5 S _ C P U
D R A M P W R G D _ C P U
R 1 34 R 1 5 7
1 . 1 K _ 1% _ 0 4 *1 .5 K _ 1% _ 0 4
V D D P W R G OO D _ R
R 1 58
3 K _ 1 %_ 0 4
( CLK,MISC,JTAG )
U 4 0 B
H _C OM P 3 A T 2 3
C O MP 3
H _C OM P 2 A T 2 4
C O MP 2
H _C OM P 1 G1 6
C O MP 1
H _C OM P 0 A T 2 6
C O MP 0
A H 2 4
S K T OC C #
H _C A T E R R # A K 1 4
C A T E R R #
R 1 21 0 _0 4 A T 1 5
H _ P E C I
P E C I
H _P R OC H O T# _ D A N 2 6
0 _ 0 4
P R O C H OT #
A K 1 5
T H E R MT R IP #
A P 2 6
H _C P U R S T #
R E S E T_ O B S #
A L 1 5
P M_ S Y N C
*0 _ 04 S Y S _A GE N T_ P W R OK A N 1 4
V C C P W R GOO D _ 1
* 10 m i l _ s h ort
A N 2 7
V C C P W R GOO D _ 0
* 10 m i l _ s h ort V D D P W R GO OD _R A K 1 3
S M_ D R A M P W R O K
A M1 5
V T TP W R G OO D
H _P W R GD _ XD P A M2 6
T A P P W R G OO D
A L 1 4
1 . 5K _ 1 % _0 4 P L T _R S T # _R
R S T I N #
R 1 55
7 5 0 _1 % _ 04 P Z 9 8 9 27 -3 6 41 -0 1 F
1 . 5V
R 2 4 6
*1 K _ 04
R 25 0 0 _ 04
D D R 3_ D R A M R S T # D S
10 ,1 1 D D R 3 _ D R A MR S T #
Q 32
* MT N 7 0 0 2Z H S 3
R 2 34 *0 _ 0 4
24 D R A M R S T _ C N TR L _P C H
9 D R A M R S T _ C N TR L
C 3 6 0
*4 7 0 p _5 0 V _ X7 R _0 4
DDR3 Compensation Signals
A 1 6
B C LK _C P U _ P 2 4
B C L K
B 1 6 S M _R C O MP _ 0
B C L K # B C LK _C P U _ N 24
A R 3 0 S M _R C O MP _ 1
B C L K _ IT P
A T 3 0
B C L K _ I T P #
S M _R C O MP _ 2
E 1 6
C LK _ E X P _ P 2 0
P E G _C L K
D 1 6
P E G _ C L K # C LK _ E X P _ N 20
A 1 8
D P L L _ R E F _ S S C L K C LK _ D P _ P 2 0
A 1 7
C LK _ D P _ N 2 0
D P LL _ R E F _S S C L K #
F 6
C P U _D R A MR S T#
S M_ D R A M R S T #
1. 1 V S _ V T T
A L 1
S M _ R C O MP _ 0
S M_ R C OM P [ 0 ]
A M1 S M _ R C O MP _ 1 R 13 0 1 0K _ 0 4
S M_ R C OM P [ 1 ] A N 1
S M _ R C O MP _ 2 R 13 1 1 0K _ 0 4
S M_ R C OM P [ 2 ]
A N 1 5
P M _ E XT T S # [ 0 ] R 15 3 *0 _ 04
P M_ E X T_ T S # [ 0 ]
A P 1 5 P M _ E XT T S # [ 1 ]
R 12 9 *0 _ 04
P M_ E X T_ T S # [ 1 ]
R 12 8 *1 2 . 4 K _1 % _ 04
A T 2 8
P R D Y #
A P 2 7 X D P _P R E Q#
P R E Q #
A N 2 8 X D P _T C L K
T C K A P 2 8
X D P _T MS
T M S
A T 2 7 X D P _T R S T# X D P _ TM S
R 6 8
T R S T #
X D P _ TD O_ M R 4 18
A T 2 9 X D P _T D I _R X D P _ TD I _ R
R 6 7
T D I
A R 2 7 X D P _ P R E Q # R 6 9
T D O
A R 2 9 X D P _T D I _M
T D I _ M
A P 2 9 X D P _T D O _ M
T D O_ M
A N 2 5 X D P _ TC LK R 6 0
D B R #
X D P _ TR S T #
R 1 08
A J 2 2
B P M# [ 0 ]
A K 2 2
B P M# [ 1 ]
A K 2 4
B P M# [ 2 ]
A J 2 4
B P M# [ 3 ]
A J 2 5 X D P _ T D O _M
R 4 1 6 *1 0 m i l _ s ho rt
B P M# [ 4 ]
A H 2 2
B P M# [ 5 ]
A K 2 3
B P M# [ 6 ]
A H 2 3
B P M# [ 7 ]
21 , 4 1 1. 1V S _V T T _ P W R G D
3. 3 V
3 .3 V
R 1 63
* 10 K _ 0 4
R 1 6 2
*1 0 K _0 4 Q 1 3
+1 . 5 S _ C P U
G
* MT N 7 0 0 2Z H S 3
B Q1 2
*2 N 3 9 0 4
C P U _D R A M R S T #
1 . 1V S _V T T 2 ,6 , 7, 19 ,2 0 , 21 , 2 4 ,2 5, 2 6 , 3 9,4 1 , 4 2 , 43
R 2 4 1
+ 1.5 S _ C P U 7 , 3 7
1 . 5V 1 0,1 1 ,3 1 , 37 , 4 0
*1 0 0K _0 4
3 . 3V 3 , 12 ,1 3 ,1 7, 1 9 , 2 0,2 1 , 2 3 , 24 ,2 6 ,2 8, 2 9 , 3 1, 3 2 , 3 3 , 34 ,3 7 ,39 , 4 0 ,4 1, 4 4
Schematic Diagrams
R 4 41 1 0 0_ 1 % _0 4
R 4 40 2 4 . 9_ 1 % _0 4
R 4 39 1 3 0_ 1 % _0 4
P M_ E X T T S #_ E C 3
T S # _D I MM 0_ 1 1 0 , 11
Sheet 4 of 53
1 . 1V S _V T T
CPU 2/7
*5 1 _ 04
5 1_ 0 4
*5 1 _ 04
*5 1 _ 04
(CLK, MISC, JTAG)
*5 1 _ 04
5 1_ 0 4
XD P _ TD I_ M
3 . 3V
C 2 2 2 *.1 u _ 10 V _ X 7 R _ 0 4
U 1 1
*7 4 A H C 1 G0 8 GW
1
4
D R A MP W R GD _ C P U
2
+1 . 5 S _ C P U _ P W R G D 4 0
CPU 2/7 (CLK, MISC, JTAG) B - 5