Figure 2-7. Address Handler Timing Diagram - National Instruments SCXI-1163 User Manual

Chapter 2
To write to the Address Handler, follow these steps:
1. Initial conditions:
SS* asserted low.
SERDATIN = don't care.
DAQD*/A = 1 (indicates data will be written to the Address Handler).
SLOT0SEL* = 1.
SERCLK = 1 (and has not transitioned since SS* went low).
2. For each bit to be written, and starting with the MSB, perform the following actions (these
bits are the address of the register of interest):
Establish the desired SERDATIN level corresponding to this bit.
SERCLK = 0.
SERCLK = 1. This rising edge clocks the data.
3. Pull DAQD*/A low to deselect the Address Handler and select the register that had its
address written to the Address Handler. This selects a register for writing to or reading from.
Figure 2-7 illustrates a write to the SCXI-1163 Address Handler of the binary pattern:
00000000 00000001
This pattern is the address of the Data Register.
DAQD*/A
SERCLK
SERDATIN
After the Address Handler has been written to, an address line of a register has been asserted. At
that stage you can write to the SCXI-1163 Data Register and read from its Module ID Register
or Status Registers using the following protocols. The contents of the Module ID Register are
reinitialized by deasserting Slot-Select. After the 32 bits of data are read from the Module ID
Register, further data will be zeros until reinitialization occurs. The Data Register latches its data
to the outputs when it is deselected.
© National Instruments Corporation
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
T SERCLK last rising edge to DAQD*/A low
delay

Figure 2-7. Address Handler Timing Diagram

2-21
Configuration and Installation
T
delay
425 nsec
SCXI-1163 User Manual