12. T
ECHNICAL APPENDIX
12.1
MULTISYSTEM PARALLEL ADAPTOR PC819
The Multi-system adaptor board PC819 is designed to allow parallel connection of two or more POWER
PLUS systems.
When several POWER PLUS systems are connected in parallel, one of the systems becomes the "master"
and other are "slaves". There is no dedicated master system: any of the systems could be master but only
one of the systems is master at a given moment. In practice, the first system that finds itself normal after
start-up, takes up the master function.
This board is installed in each POWER PLUS controller unit and is connected to the common signal bus.
The signal bus includes the following signals used for the unit's synchronization and load sharing between
the units:
•
master_sys: Bi-directional line that is in "0" status if any unit is master and "1" if all the units are
slaves
•
pll_data_sys: bi-directional signal of UART with baud rate 9600. Using this line, the master
transmits to slaves it's inverter frequency value for each period of inverter's frequency. All the
slaves receive this signal and use it to build their reference inverter's signals
•
pll_sync_bus: bi-directional line for pulse with duration ~220uS that the master sends to mark the
zero cross of it's inverter voltage in phase R. This pulse is used by slaves to synchronize them to
master
•
load_to_byp command: any unit that want to transfer the load to bypass sends this command to all
the units. The transferring is performed after acknowledge from all the units
•
load_on_byp: acknowledge signal means that bypass contactor of any unit is activated
•
load_on_inv: acknowledge signal means that inverter's contactor of any unit is activated
•
cur_shar_r: analog voltage in range 0-5V proportional to average current of all UPS modules in
phase R. This signal is used by all UPS modules for active current sharing: the modules change
their phase R voltage in specified limits to achieve the equal load currents
•
cur_shar_s: analog voltage in range 0-5V proportional to average current of all UPS modules in
phase S. This signal is used by all UPS modules for active current sharing: the modules change
their phase S voltage in specified limits to achieve the equal load currents
•
cur_shar_t: analog voltage in range 0-5V proportional to average current of all UPS modules in
phase T. This signal is used by all UPS modules for active current sharing: the modules change
their phase T voltage in specified limits to achieve the equal load currents
The PC819 board consists of microcontroller IC2 that defines the master /slave status of the unit, opto-
couplers ISO2-ISO6 which manage bi-directional pll_synchronization, and pll_data lines and 5V stabilizer
IC1.
The microcontroller reads the status of master_sys line and if it finds it in logic "1" status, takes up the
master function for its unit.
Opto-couplers ISO2-ISO6 are controlled by the master signal of the microcontroller: the master is
configured to transmit the signals and the slave- to receive them.
In a Triple-Parallel system, the units are connected in a ring. Each unit's adaptor board is connected to the
adaptor boards of each of the other two units by means of a double cable. In the event of a break in one of
the signal cables, the second cable enables the parallel system to continue normal operation.
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UPS,
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. 2.0
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