Lvds Interface - Eurotech Titan User Manual

LVDS interface

There is an optional Low-Voltage Differential Signalling (LVDS) interface available on the
TL
TITAN. LVDS combines high data rates with low power consumption. The benefits of
LVDS include low-voltage power supply compatibility, low noise generation, high noise
rejection and robust transmission signals.
The National Semiconductor transmitter DS90C363 is used to convert 16 bits of LCD
data signals into three LVDS data streams. A phase-locked transmit clock is transmitted
in parallel with the data streams over a fourth LVDS link. The LVDS signals are routed to
the connector J8. For connector details see the section
The LVDS transmitter is enabled using the signal LVDS_EN (GPIO 21). Details are
shown in the following table:
LVDS_EN
(GPIO 21)
0
1
The LVDS transmitter can be programmed for rising edge strobe or falling edge
strobe operation through a signal LVDS_FES# (GPIO 27). This is shown below:
LVDS_FES#
(GPIO 27)
0
1
If the FPIF-LVDS-TX is to be connected directly to an LVDS display via the Hirose
connector J2, then this link selects the displays LVDS Receiver input map. Fitting or not
fitting a jumper to JP3 sets J2 pin 20 (MSL) to 3.3V or GND (default) respectively.
When the LVDS interface is used, connector LK3 on JP3 should be set to the
correct setting for the display. See section
LK3 on JP3, page 79, for details. Please consult the manual of your LVDS
display for which setting to use for the National Semiconductor DS90C383 LVDS
Transceiver.
Connector
backlight inverter when the LVDS interface is used. See the section
connector, page 68, for J4 pin assignment and connector details.
Issue D
Selected LVDS function
LVDS power down (default)
LVDS enable
Selected LVDS function
Falling edge strobe
Rising edge strobe (default)
should be used to supply the power and brightness control for the
J4
Detailed hardware description
J8 – LVDS connector, page 71.
LVDS mode select [MSL] jumper –
J4 – LCD
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