Intermec CK30 Service Manual page 81

Chapter 4 — Theory of Operation
SDRAM Controller
When the PCI card initiates a PCI transaction to read data from system
SDRAM or write data to it, the PCI bridge raises the SA_BREQ signal to
request the system bus from PXA255. When the PXA255 has completed
any pending operations, it raises SA_BGNT to signal the FPGA to take
over the bus as an alternate bus master. The SDRAM controller in the
FPGA takes over for the PXA255 SDRAM controller according to the
®
handoff procedure detailed in the Intel PXA255 Processor Developer's
Manual.
The FPGA SDRAM controller is set up in advance by software for the
appropriate SDRAM density. It runs the SDRAM at 49.77MHz–half the
rate used by the PXA255 SDRAM controller. The FPGA controller keeps
the CAS latency set to 2 but resets the SDRAM burst length to full-page
mode so it can perform variable-length bursts. A single SDRAM burst of
up to 8 words is then performed. The burst length is limited to 8 as a
simple way of ensuring that the FPGA does not hog the bus for too long
and to avoid the complication of adding SDRAM refresh control to the
FPGA. When the burst is complete, the FPGA SDRAM controller sets the
SDRAM back to its previous burst length setting of four.
PCI Bus Mastering
CK30 Handheld Computer Service Manual 71