Debug Board - Intermec CK30 Service Manual

Chapter 4 — Theory of Operation

Debug Board

94
19 1
20 2
FPGA JTAG
CPU JTAG
TARGET
SYSTEM
FLEX
To P1 on
target system
073048 JTAG Board and 073049 flex
J33, J34 and J35 are 3 high-density 40-pin SMT board-to-board
connectors providing debug board access to the CK30 system bus and
control signals. These connectors are not installed on production boards,
and so are not intended as a field debug facility, but could be soldered
onto a production board to help diagnose a field problem as a last resort.
The signal set brought out through these connectors includes:
• SA_MD31:0 (data bus)
• SA_MA25:0 (addr bus)
• Control signals RD/WR*, WE*, OE*, PWE*, RESET_IN*, DQM3:0,
RDY
• SCAN_DREQ, PCI_IRQ, SA_BREQ, SA_BGNT
• SDRAM control signals SDCAS*, SDRAS*, SDCS0*, SDCKE
• Clocks SDCLK, FPGA_CLK
• Chip selects FPGA_CS*, FLASH_CS*, PCI/HCR_CS*
PIC PROGRAMMER
I2C
RESET
CK30 Handheld Computer Service Manual