Fpga Bus Interface; Fpga Clocks - Intermec CK30 Service Manual

Chapter 4 — Theory of Operation

FPGA Bus Interface

FPGA Clocks

50
Software is responsible for shutting off FPGA core power in a critical
battery situation. If FPGA power is still on when the system suspends, it
will be shut off in hardware by the "Type 2" interlock mechanism
described in "Device Power Control" on page 58.
The FPGA occupies PXA255 memory areas 2 and 5 (chip selects
HCR/PCI_CS* and FPGA_CS*). Both chip selects are set up as Variable
Latency IO areas. The FPGA also combines these chip selects with the
PWE* strobe to create the write strobes for HCR registers U11 and U16.
For this reason, U11 and U16 cannot be written to until the FPGA is
downloaded.
Clock Source
As noted in "System Clocks" on page 41, the clock source for the FPGA is
FPGA_CLK, the 49.77MHz SDCLK2 output from the PXA255.
Scanner I/F
Internal buffered versions of FPGA_CLK directly clock the count
gathering logic, scanner control state machine, FIFOs, and DMA buffer.
Another clock domain exists on the scanner interface side of this logic
because of the 13.5MHz PIXCLK on the 2D imager.
PCI Bridge
Because the bus interface side of the PCI bridge includes an SDRAM
controller, skew must be minimized between the internal 49.77MHz clock
and SDCLK (also 49.77MHz when the FPGA owns the bus). This
minimization is done by bringing out a copy of SDCLK (CLK_OUT),
delaying it through a trace of length equal to the SDCLK run from FPGA
to SDRAM, and bringing it back as feedback into one of the FPGA
internal DLLs (Delay-Locked Loop) to de-skew FPGA_CLK.
The 24.885MHz PCI bus clock output (PCI_CLK) is derived (divide by
2) from this de-skewed FPGA_CLK. The LogiCore PCI interface used in
the bridge is clocked from this external PCI_CLK, rather than from an
internal copy of it, so that the bridge sees the same clock as the PCI card.
As with CLK_OUT, the PCLK etch length is kept approximately the same
as the PCI_CLK trace to the card to minimize skew.
CK30 Handheld Computer Service Manual